參數(shù)資料
型號(hào)： A42MX24-3TQ100B
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁(yè)數(shù)： 57/93頁(yè)
文件大小： 854K
代理商： A42MX24-3TQ100B
60
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
A15 /
CLK_SEL_1
A15 (MSB)
C10
16-bit bi-directional address bus.
For 64K RAM versions, this signal is always configured as address
line A15 (MSB). Refer to the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this
signal operates as address line A15.
For 4K RAM versions, if UPADDREN is connected to logic "0", this signal
operates as CLK_SEL_1. In this case, A15/CLK_SEL_1 and
A14/CLK_SEL_0 are used to select the Mark3 clock frequency, as follows:
CLK_SEL_1
CLK_SEL_0
Clock Frequency
0
10 MHz
0
1
20 MHz
1
0
12 MHz
1
16 MHz
TABLE 61. PROCESSOR ADDRESS BUS
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B3
BALL
A11
A14 /
CLK_SEL_0
A14
A10
For 64K RAM versions, this signal is always configured as address
line A14. Refer to the description of A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this
signal operates as A14.
For 4K RAM versions, if UPADDREN is connected to logic "0", then
this signal operates as CLK_SEL_0. In this case, CLK_SEL_1 and
CLK_SEL_0 are used to select the Mark3 clock frequency, as defined
in the description for A15/CLK_SEL1 above.
A7
A13 /
LOGIC “1”
A13
B10
For 64K RAM versions, this signal is always configured as address
line A13. Refer to the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this
signal operates as A13.
For 4K RAM versions, if UPADDREN is connected to logic "0", then
this signal MUST be connected to +3.3V-LOGIC (logic "1").
B10
A12 /
RTBOOT
A12
A9
For 64K RAM versions, this signal is always configured as address
line A12. Refer to the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this
signal operates as A12.
For 4K RAM versions, if UPADDREN is connected to logic "0", then
this signal functions as RTBOOT. If RTBOOT is connected to logic "0",
the Mark3 will initialize in RT mode with the Busy status word bit set
following power turn-on. If RTBOOT is hardwired to logic "1", the
Mark3 will initialize in either Idle mode (for an RT-only part), or in BC
mode (for a BC/RT/MT part).
A10
BU-64743B8
BU-64843B8
BU-64863B8
BALL
4K RAM
(BU-64743B8
BU-6484XBX)
64K RAM
(BU-6486XBX)
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
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A42MX24-3TQ176 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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A42MX24-3TQG176 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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