參數(shù)資料
型號： A42MX24-3BG100B
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Bus Transceivers With 3-State Outputs 20-PDIP -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 62/123頁
文件大?。?/td> 854K
代理商： A42MX24-3BG100B
40MX and 42MX FPGA Families
1-56
v6.0
Table 34
A42MX16 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Logic Module Propagation Delays
1
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
t
PD1
Single Module
1.4
1.5
1.7
2.0
2.8
ns
t
CO
Sequential Clock-to-Q
1.4
1.6
1.8
2.1
3.0
ns
t
GO
Latch G-to-Q
1.4
1.5
1.7
2.0
2.8
ns
t
RS
Logic Module Predicted Routing Delays
2
Flip-Flop (Latch) Reset-to-Q
1.6
1.7
2.0
2.3
3.3
ns
t
RD1
FO=1 Routing Delay
0.8
0.9
1.0
1.2
1.6
ns
t
RD2
FO=2 Routing Delay
1.0
1.2
1.3
1.5
2.1
ns
t
RD3
FO=3 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
t
RD4
FO=4 Routing Delay
1.6
1.7
2.0
2.3
3.2
ns
t
RD8
Logic Module Sequential Timing
3,4
FO=8 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
t
SUD
Flip-Flop (Latch) Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
t
HD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
t
HENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t
WCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.4
3.8
4.3
5.0
7.1
ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.5
5.0
5.6
6.6
9.2
ns
t
A
Flip-Flop Clock Input Period
6.8
7.6
8.6
10.1
14.1
ns
t
INH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
INSU
Input Buffer Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
t
OUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
OUTSU
Output Buffer Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
f
MAX
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Flip-Flop (Latch) Clock Frequency
215
195
179
156
94
MHz
相關(guān)PDF資料
PDF描述
A42MX24-3BG100ES 40MX and 42MX FPGA Families
A42MX24-3BG100I 40MX and 42MX FPGA Families
A42MX24-3BG100M 40MX and 42MX FPGA Families
A42MX24-3CQ100 40MX and 42MX FPGA Families
A42MX24-3CQ100A Octal Bus Transceivers With 3-State Outputs 20-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
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