參數(shù)資料
型號： A42MX24-2PL100A
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 76/123頁
文件大?。?/td> 854K
代理商： A42MX24-2PL100A
40MX and 42MX FPGA Families
1-70
v6.0
Synchronous SRAM Operations (Continued)
t
ADH
t
RENSU
t
RENH
t
WENSU
t
WENH
t
BENS
t
BENH
Asynchronous SRAM Operations
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
Read Enable Set-Up
0.6
0.7
0.8
0.9
1.3
ns
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Block Enable Set-Up
2.8
3.1
3.5
4.1
5.7
ns
Block Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t
RPD
t
RDADV
t
ADSU
t
ADH
t
RENSUA
Asynchronous Access Time
8.1
9.0
10.2
12.0
16.8
ns
Read Address Valid
8.8
9.8
11.1
13.0
18.2
ns
Address/Data Set-Up Time
1.6
1.8
2.0
2.4
3.4
ns
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
Read Enable Set-Up to Address
Valid
0.6
0.7
0.8
0.9
1.3
ns
t
RENHA
t
WENSU
t
WENH
t
DOH
Input Module Propagation Delays
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Data Out Hold Time
1.2
1.3
1.5
1.8
2.5
ns
t
INPY
t
INGO
t
INH
t
INSU
t
ILA
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Input Data Pad-to-Y
1.0
1.1
1.3
1.5
2.1
ns
Input Latch Gate-to-Output
1.4
1.6
1.8
2.1
2.9
ns
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
Input Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
Table 38
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
相關(guān)PDF資料
PDF描述
A42MX24-2PL100B 40MX and 42MX FPGA Families
A42MX24-2PL100ES 40MX and 42MX FPGA Families
A42MX24-2PL100I Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85
A42MX24-2PL100M Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85
A42MX24-2PQ100I 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX24-2PL84 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-2PL84I 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-2PLG84 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-2PLG84I 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-2PQ160 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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