參數(shù)資料
型號(hào)： A42MX24-1VQ100I
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 79/123頁
文件大?。?/td> 854K
代理商： A42MX24-1VQ100I
40MX and 42MX FPGA Families
v6.0
1-73
Table 39
A42MX36 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 3.0V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Logic Module Combinatorial Functions
1
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
PD
t
PDD
Logic Module Predicted Routing Delays
2
Internal Array Module Delay
1.9
2.1
2.3
2.7
3.8
ns
Internal Decode Module Delay
2.2
2.5
2.8
3.3
4.7
ns
t
RD1
t
RD2
t
RD3
t
RD4
t
RD5
t
RDD
Logic Module Sequential Timing
3, 4
FO=1 Routing Delay
1.3
1.5
1.7
2.0
2.7
ns
FO=2 Routing Delay
1.8
2.0
2.3
2.7
3.7
ns
FO=3 Routing Delay
2.3
2.5
2.8
3.4
4.7
ns
FO=4 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
FO=8 Routing Delay
4.6
5.2
5.8
6.9
9.6
ns
Decode-to-Output Routing Delay
0.5
0.5
0.6
0.7
1.0
ns
t
CO
t
GO
t
SUD
t
HD
t
RO
t
SUENA
t
HENA
t
WCLKA
Flip-Flop Clock-to-Output
1.8
2.0
2.3
2.7
3.7
ns
Latch Gate-to-Output
1.8
2.0
2.3
2.7
3.7
ns
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Reset-to-Output
2.2
2.4
2.7
3.2
4.5
ns
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Clock Active
Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.1
6.8
7.7
9.0
12.6
ns
Synchronous SRAM Operations
t
RC
t
WC
t
RCKHL
t
RCO
t
ADSU
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Read Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
Write Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
Clock HIGH/LOW Time
4.8
5.3
6.0
7.0
9.8
ns
Data Valid After Clock HIGH/LOW
4.8
5.3
6.0
7.0
9.8
ns
Address/Data Set-Up Time
2.3
2.5
2.8
3.4
4.8
ns
相關(guān)PDF資料
PDF描述
A42MX24-1VQ100M Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-PDIP -40 to 85
A42MX24-2BG100M Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SO -40 to 85
A42MX24-2CQ100I Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SO -40 to 85
A42MX24-2CQ100M 40MX and 42MX FPGA Families
A42MX24-2PL100 Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85
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A42MX24-2PLG84 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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