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參數(shù)資料
型號： A42MX24-1TQ176I
廠商： Microsemi SoC
文件頁數(shù)： 108/142頁
文件大?。?/td> 0K
描述： IC FPGA MX SGL CHIP 36K 176-TQFP
標(biāo)準(zhǔn)包裝： 40
系列： MX
輸入/輸出數(shù)： 150
門數(shù)： 36000
電源電壓： 3 V ~ 3.6 V，4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 176-LQFP
供應(yīng)商設(shè)備封裝： 176-TQFP（24x24）
40MX and 42MX FPGA Families
1- 64
R e v i sio n 1 1
Table 1-35 A42MX16 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays1
tPD1
Single Module
1.9
2.1
2.4
2.8
4.0
ns
tCO
Sequential Clock-to-Q
2.0
2.2
2.5
3.0
4.2
ns
tGO
Latch G-to-Q
1.9
2.1
2.4
2.8
4.0
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.2
2.4
2.8
3.3
4.6
ns
Logic Module Predicted Routing Delays2
tRD1
FO = 1 Routing Delay
1.1
1.2
1.4
1.6
2.3
ns
tRD2
FO = 2 Routing Delay
1.5
1.6
1.8
2.1
3.0
ns
tRD3
FO = 3 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
tRD4
FO = 4 Routing Delay
2.2
2.4
2.7
3.2
4.5
ns
tRD8
FO = 8 Routing Delay
3.6
4.0
4.5
5.3
7.5
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch)
Data Input Set-Up
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
4.8
5.3
6.0
7.1
9.9
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
6.2
6.9
7.9
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
9.5
10.6
12.0
14.1
19.8
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.7
0.8
0.9
1.01
1.4
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.7
0.8
0.89
1.01
1.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
129
117
108
94
56
MHz
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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參數(shù)描述
A42MX24-1TQ176M 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 176TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 150 I/O 176TQFP
A42MX24-1TQG176 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-1TQG176I 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-1TQG176M 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 36K Gates 912 Cells 0.45um Technology 3.3V/5V 176-Pin TQFP 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 176TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP
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