tRENSU Read Enable Set-Up 0.6 0.7 0.8 0.9 1.3 ns
參數(shù)資料
型號： A42MX24-1PQ160
廠商： Microsemi SoC
文件頁數(shù)： 120/142頁
文件大?。?/td> 0K
描述： IC FPGA MX SGL CHIP 36K 160-PQFP
標準包裝： 24
系列： MX
輸入/輸出數(shù)： 125
門數(shù)： 36000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
40MX and 42MX FPGA Families
Re vi s i on 11
1 - 75
tRENSU
Read Enable Set-Up
0.6
0.7
0.8
0.9
1.3
ns
tRENH
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
ns
tBENS
Block Enable Set-Up
2.8
3.1
3.5
4.1
5.7
ns
tBENH
Block Enable Hold
0.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
8.1
9.0
10.2
12.0
16.8
ns
tRDADV
Read Address Valid
8.8
9.8
11.1
13.0
18.2
ns
tADSU
Address/Data Set-Up Time
1.6
1.8
2.0
2.4
3.4
ns
tADH
Address/Data Hold Time
0.0
ns
tRENSUA Read Enable Set-Up to Address
Valid
0.6
0.7
0.8
0.9
1.3
ns
tRENHA
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
ns
tDOH
Data Out Hold Time
1.2
1.3
1.5
1.8
2.5
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.0
1.1
1.3
1.5
2.1
ns
tINGO
Input Latch Gate-to-Output
1.4
1.6
1.8
2.1
2.9
ns
tINH
Input Latch Hold
0.0
ns
tINSU
Input Latch Set-Up
0.5
0.6
0.7
1.0
ns
tILA
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
tIRD2
FO = 2 Routing Delay
2.3
2.6
2.9
3.4
4.8
ns
tIRD3
FO = 3 Routing Delay
2.6
2.9
3.3
3.9
5.5
ns
tIRD4
FO = 4 Routing Delay
3.0
3.3
3.8
4.4
6.2
ns
tIRD8
FO = 8 Routing Delay
4.3
4.8
5.5
6.4
9.0
ns
Table 1-38 A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min.
Max. Units
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX24-1PQ160I 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-1PQ160M 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 160PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 125 I/O 160PQFP
A42MX24-1PQ208 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-1PQ208I 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-1PQ208M 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 208PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 176 I/O 208PQFP
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