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    • 參數(shù)資料
      型號: A42MX24-1PL100B
      廠商: Electronic Theatre Controls, Inc.
      英文描述: 40MX and 42MX FPGA Families
      中文描述: 40MX和42MX FPGA系列
      文件頁數(shù): 49/123頁
      文件大?。?/td> 854K
      代理商: A42MX24-1PL100B
      40MX and 42MX FPGA Families
      v6.0
      1-43
      Input Module Predicted Routing Delays
      1
      t
      IRD1
      FO=1 Routing Delay
      2.1
      2.4
      2.2
      3.2
      4.5
      ns
      t
      IRD2
      FO=2 Routing Delay
      2.6
      3.0
      3.4
      4.0
      5.6
      ns
      t
      IRD3
      FO=3 Routing Delay
      3.1
      3.6
      4.1
      4.8
      6.7
      ns
      t
      IRD4
      FO=4 Routing Delay
      3.6
      4.2
      4.8
      5.6
      7.8
      ns
      t
      IRD8
      Global Clock Network
      FO=8 Routing Delay
      5.7
      6.6
      7.5
      8.8
      12.4
      ns
      t
      CKH
      Input Low to HIGH
      FO = 16
      FO = 128
      4.6
      4.6
      5.3
      5.3
      6.0
      6.0
      7.0
      7.0
      9.8
      9.8
      ns
      t
      CKL
      Input High to LOW
      FO = 16
      FO = 128
      4.8
      4.8
      5.6
      5.6
      6.3
      6.3
      7.4
      7.4
      10.4
      10.4
      ns
      t
      PWH
      Minimum
      Width HIGH
      Pulse
      FO = 16
      FO = 128
      2.2
      2.4
      2.6
      2.7
      2.9
      3.1
      3.4
      3.6
      4.8
      5.1
      ns
      t
      PWL
      Minimum
      Width LOW
      Pulse
      FO = 16
      FO = 128
      2.2
      2.4
      2.6
      2.7
      2.9
      3.01
      3.4
      3.6
      4.8
      5.1
      ns
      t
      CKSW
      Maximum Skew
      FO = 16
      FO = 128
      0.4
      0.5
      0.5
      0.6
      0.5
      0.7
      0.6
      0.8
      0.8
      1.2
      ns
      t
      P
      Minimum Period
      FO = 16
      FO = 128
      4.7
      4.8
      5.4
      5.6
      6.1
      6.3
      7.2
      7.5
      10.0
      10.4
      ns
      f
      MAX
      Maximum
      Frequency
      FO = 16
      FO = 128
      188
      181
      175
      168
      160
      154
      139
      134
      83
      80
      MHz
      TTL Output Module Timing
      4
      t
      DLH
      Data-to-Pad HIGH
      3.3
      3.8
      4.3
      5.1
      7.2
      ns
      t
      DHL
      Data-to-Pad LOW
      4.0
      4.6
      5.2
      6.1
      8.6
      ns
      t
      ENZH
      Enable Pad Z to HIGH
      3.7
      4.3
      4.9
      5.8
      8.0
      ns
      t
      ENZL
      Enable Pad Z to LOW
      4.7
      5.4
      6.1
      7.2
      10.1
      ns
      t
      ENHZ
      Enable Pad HIGH to Z
      7.9
      9.1
      10.4
      12.2
      17.1
      ns
      t
      ENLZ
      Enable Pad LOW to Z
      5.9
      6.8
      7.7
      9.0
      12.6
      ns
      d
      TLH
      Delta LOW to HIGH
      0.02
      0.02
      0.03
      0.03
      0.04
      ns/pF
      d
      THL
      Delta HIGH to LOW
      0.03
      0.03
      0.03
      0.04
      0.06
      ns/pF
      Table 30
      A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued)
      (Worst-Case Commercial Conditions, V
      CC
      = 4.75V, T
      J
      = 70°C)
      ‘–3’ Speed
      ‘–2’ Speed
      ‘–1’ Speed
      ‘Std’ Speed
      ‘–F’ Speed
      Units
      Parameter Description
      Min.
      Max.
      Min.
      Max.
      Min.
      Max.
      Min.
      Max.
      Min.
      Max.
      Notes:
      1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
      device performance. Post-route timing analysis or simulation is required to determine actual performance.
      2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
      3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
      time for this macro.
      4. Delays based on 35 pF loading.
      相關(guān)PDF資料
      PDF描述
      A42MX24-1PL100ES 40MX and 42MX FPGA Families
      A42MX24-1PL100I 40MX and 42MX FPGA Families
      A42MX24-1PL100M 40MX and 42MX FPGA Families
      A42MX24-1PQ100ES 40MX and 42MX FPGA Families
      A42MX24-1PQ100I 40MX and 42MX FPGA Families
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