參數(shù)資料
型號： A42MX16-FVQ100B
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 67/123頁
文件大小： 854K
代理商： A42MX16-FVQ100B
40MX and 42MX FPGA Families
v6.0
1-61
TTL Output Module Timing
5
t
DLH
t
DHL
t
ENZH
t
ENZL
t
ENHZ
t
ENLZ
t
GLH
t
GHL
t
LCO
Data-to-Pad HIGH
3.5
3.9
4.4
5.2
7.3
ns
Data-to-Pad LOW
4.1
4.6
5.2
6.1
8.6
ns
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
G-to-Pad HIGH
4.8
5.3
6.0
7.2
10.0
ns
G-to-Pad LOW
4.8
5.3
6.0
7.2
10.0
ns
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
t
ACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
d
TLH
d
THL
CMOS Output Module Timing
5
Capacitive Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08
ns/pF
Capacitive Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10
ns/pF
t
DLH
t
DHL
t
ENZH
t
ENZL
t
ENHZ
t
ENLZ
t
GLH
t
GHL
t
LCO
Data-to-Pad HIGH
4.5
5.0
5.6
6.6
9.3
ns
Data-to-Pad LOW
3.4
3.8
4.3
5.1
7.1
ns
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
G-to-Pad HIGH
7.1
7.9
8.9
10.5
14.7
ns
G-to-Pad LOW
7.1
7.9
8.9
10.5
14.7
ns
I/O Latch Clock-to-Out (Pad-to-
Pad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
t
ACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
d
TLH
d
THL
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Capacitive Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08
ns/pF
Capacitive Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10
ns/pF
Table 35
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
CCA
= 3.0V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
相關(guān)PDF資料
PDF描述
A42MX16-FVQ100ES Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FVQ100I Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FVQ100M 40MX and 42MX FPGA Families
A42MX24 Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-PDIP -40 to 85
A42MX24-1VQ100I 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-FVQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FVQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FVQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FVQG100 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17）
A42MX16-PL100 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*