參數(shù)資料
型號： A42MX16-FTQ100A
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 82/123頁
文件大?。?/td> 854K
代理商： A42MX16-FTQ100A
40MX and 42MX FPGA Families
1-76
v6.0
TTL Output Module Timing
5
t
ENLZ
t
GLH
t
GHL
t
LSU
t
LH
t
LCO
Enable Pad LOW to Z
6.9
7.6
8.7
10.2
14.3
ns
G-to-Pad HIGH
4.9
5.5
6.2
7.3
10.2
ns
G-to-Pad LOW
4.9
5.5
6.2
7.3
10.2
ns
I/O Latch Output Set-Up
0.7
0.7
0.8
1.0
1.4
ns
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
7.9
8.8
10.0
11.8
16.5
ns
t
ACO
Array Latch Clock-to-Out (Pad-
to-Pad) 32 I/O
10.9
12.1
13.7
16.1
22.5
ns
d
TLH
d
THL
CMOS Output Module Timing
5
Capacitive Loading, LOW to HIGH
0.10
0.11
0.12
0.14
0.20
ns/pF
Capacitive Loading, HIGH to LOW
0.10
0.11
0.12
0.14
0.20
ns/pF
t
DLH
t
DHL
t
ENZH
t
ENZL
t
ENHZ
t
ENLZ
t
GLH
t
GHL
t
LSU
t
LH
t
LCO
Data-to-Pad HIGH
4.9
5.5
6.2
7.3
10.3
ns
Data-to-Pad LOW
3.4
3.8
4.3
5.1
7.1
ns
Enable Pad Z to HIGH
3.7
4.1
4.7
5.5
7.7
ns
Enable Pad Z to LOW
4.1
4.6
5.2
6.1
8.5
ns
Enable Pad HIGH to Z
7.4
8.2
9.3
10.9
15.3
ns
Enable Pad LOW to Z
6.9
7.6
8.7
10.2
14.3
ns
G-to-Pad HIGH
7.0
7.8
8.9
10.4
14.6
ns
G-to-Pad LOW
7.0
7.8
8.9
10.4
14.6
ns
I/O Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
7.9
8.8
10.0
11.8
16.5
ns
Table 39
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
CCA
= 3.0V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
PDF描述
A42MX16-FTQ100B Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
A42MX16-FTQ100ES Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
A42MX16-FTQ100I Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SSOP -40 to 85
A42MX16-FTQ100M Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SSOP -40 to 85
A42MX16-FVQ100 40MX and 42MX FPGA Families
相關代理商/技術參數(shù)
參數(shù)描述
A42MX16-FTQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FTQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FTQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FTQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FTQ176 功能描述:IC FPGA MX SGL CHIP 24K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17）
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