參數(shù)資料
型號： A42MX16-3PL100I
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 60/123頁
文件大小： 854K
代理商： A42MX16-3PL100I
40MX and 42MX FPGA Families
1-54
v6.0
TTL Output Module Timing
5
t
DLH
Data-to-Pad HIGH
3.4
3.8
4.3
5.1
7.1
ns
t
DHL
Data-to-Pad LOW
4.0
4.5
5.1
6.1
8.3
ns
t
ENZH
Enable Pad Z to
HIGH
3.7
4.1
4.6
5.5
7.6
ns
t
ENZL
Enable Pad Z to
LOW
4.1
4.5
5.1
6.1
8.5
ns
t
ENHZ
Enable Pad HIGH to
Z
6.9
7.6
8.6
10.2
14.2
ns
t
ENLZ
Enable Pad LOW to
Z
7.5
8.3
9.4
11.1
15.5
ns
t
GLH
G-to-Pad HIGH
5.8
6.5
7.3
8.6
12.0
ns
t
GHL
G-to-Pad LOW
5.8
6.5
7.3
8.6
12.0
ns
t
LSU
I/O Latch Set-Up
0.7
0.8
0.9
1.0
1.4
ns
t
LH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
LCO
I/O Latch Clock-to-
Out (Pad-to-Pad),
64 Clock Loading
8.7
9.7
10.9
12.9
18.0
ns
t
ACO
Array Clock-to-Out
(Pad-to-Pad),
64 Clock Loading
12.2
13.5
15.4
18.1
25.3
ns
d
TLH
Capacity
LOW to HIGH
Loading,
0.00
0.00
0.00
0.10
0.01
ns/pF
d
THL
Capacity
HIGH to LOW
Loading,
0.09
0.10
0.10
0.10
0.10
ns/pF
Table 33
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
CCA
= 3.0V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A42MX16-3PL100M Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85
A42MX16-3PQ100ES Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FPQ100B Octal Transparent D-Type Latches With 3-State Outputs 20-SO -40 to 85
A42MX16-FPQ100ES Octal Transparent D-Type Latches With 3-State Outputs 20-SO -40 to 85
A42MX16-FPQ100I Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-3PL100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3PL84 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-3PL84I 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-3PL84M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A42MX16-3PLG84 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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