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| 型號(hào)： | A42MX16-3CQ100B |
| 廠(chǎng)商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Octal Buffers and Line Drivers With 3-State Outputs 20-SSOP -40 to 85 |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 72/123頁(yè) |
| 文件大小： | 854K |
| 代理商： | A42MX16-3CQ100B |
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40MX and 42MX FPGA Families
1-66
v6.0
Table 37
A42MX24 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 3.0V, T
J
= 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Logic Module Combinatorial Functions
1
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
t
PD
Internal Array Module Delay
2.0
1.8
2.1
2.5
3.4
ns
t
PDD
Logic Module Predicted Routing Delays
2
Internal Decode Module Delay
1.1
2.2
2.5
3.0
4.2
ns
t
RD1
FO=1 Routing Delay
1.7
1.3
1.4
1.7
2.3
ns
t
RD2
FO=2 Routing Delay
2.0
1.6
1.8
2.1
3.0
ns
t
RD3
FO=3 Routing Delay
1.1
2.0
2.2
2.6
3.7
ns
t
RD4
FO=4 Routing Delay
1.5
2.3
2.6
3.1
4.3
ns
t
RD5
Logic Module Sequential Timing
3, 4
FO=8 Routing Delay
1.8
3.7
4.2
5.0
7.0
ns
t
CO
Flip-Flop Clock-to-Output
2.1
2.0
2.3
2.7
3.7
ns
t
GO
Latch Gate-to-Output
3.4
1.9
2.1
2.5
3.4
ns
t
SUD
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
t
HD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
t
RO
Flip-Flop (Latch) Reset-to-Output
2.0
2.2
2.5
2.9
4.1
ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.6
0.7
0.8
1.2
ns
t
HENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t
WCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.1
6.8
7.7
9.0
12.6
ns
Input Module Propagation Delays
t
INPY
Input Data Pad-to-Y
1.4
1.6
1.8
2.2
3.0
ns
t
INGO
Input Latch Gate-to-
Output
1.8
1.9
2.2
2.6
3.6
ns
t
INH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
INSU
Input Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
t
ILA
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Latch Active Pulse Width
6.5
7.3
8.2
9.7
13.5
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3CQ100ES | Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| A42MX16-3CQ100I | Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| A42MX16-3CQ100M | Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| A42MX16-3PL100I | Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| A42MX16-3PL100M | Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3CQ100ES | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3CQ100I | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3CQ100M | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100A | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families |
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