參數(shù)資料
型號: A42MX16-1VQ100ES
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 68/120頁
文件大?。?/td> 854K
代理商: A42MX16-1VQ100ES
51
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.11.2
External Interrupt Mask Register – EIMSK
Bits 7..2 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 1 - INT1: External INTerrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control 1 bits ISC11 and ISC10 in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt
Request 1 is executed from the INT1 Interrupt Vector.
Bit 0 - INT0: External INTerrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control 0 bits ISC01 and ISC00 in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.
3.11.3
External Interrupt Flag Register – EIFR
Bits 7..2 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 1 - INTF1: External INTerrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set
(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 is configured as a level interrupt.
Bit 0 - INTF0: External INTerrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
Bit
765
4321
0
-
INT1
INT0
EIMSK
Read/Write
R
RRRR
R
R/W
Initial Value
000
0000
0
Bit
7
654
32
10
-
INTF1
INTF0
EIFR
Read/Write
RR
R/W
Initial Value
0
000
00
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A42MX16-1VQG100I 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA(27X27)
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