參數(shù)資料
型號: A42MX09-VQ100MX79
元件分類: FPGA
英文描述: FPGA, 336 CLBS, 14000 GATES, 117 MHz, PQFP100
封裝: 1 MM HEIGHT, PLASTIC, VQFP-100
文件頁數(shù): 108/124頁
文件大?。?/td> 3142K
代理商: A42MX09-VQ100MX79
40MX and 42MX FPGA Families
1- 78
v6.1
TMS, I/O
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI and TDO pins
are boundary scan pins. Once the boundary scan pins are
in test mode, they will remain in that mode until the
internal boundary scan state machine reaches the "logic
reset" state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The "logic
reset" state is reached 5 TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications. IEEE JTAG
specification recommends a 10k
Ω pull-up resistor on the
pin. BST pins are only available in A42MX24 and
A42MX36 devices.
VCC
Supply Voltage
Input supply voltage for 40MX devices
VCCA
Supply Voltage
Supply voltage for array in 42MX devices
VCCI
Supply Voltage
Supply voltage for I/Os in 42MX devices
WD, I/O
Wide Decode Output
When a wide decode module is used in a 42MX device
this pin can be used as a dedicated output from the wide
decode
module.
This
direct
connection
eliminates
additional interconnect delays associated with regular
logic modules. To implement the direct I/O connection,
connect an output buffer of any type to the output of
the wide decode macro and place this output on one of
the reserved WD pins.
相關(guān)PDF資料
PDF描述
A42MX09-VQ100M FPGA, 336 CLBS, 14000 GATES, 117 MHz, PQFP100
A42MX09-VQ100X79 FPGA, 336 CLBS, 14000 GATES, 117 MHz, PQFP100
A42MX09-VQ100 FPGA, 336 CLBS, 14000 GATES, 117 MHz, PQFP100
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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