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參數(shù)資料
型號(hào)： A42MX09-PQ100A
廠商： Microsemi SoC
文件頁數(shù)： 119/142頁
文件大?。?/td> 0K
描述： IC FPGA MX SGL CHIP 14K 100-PQFP
標(biāo)準(zhǔn)包裝： 66
系列： MX
輸入/輸出數(shù)： 83
門數(shù)： 14000
電源電壓： 3 V ~ 3.6 V，4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-PQFP（14x20）
40MX and 42MX FPGA Families
1- 74
R e v i sio n 1 1
Table 1-38 A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min.
Max. Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
1.3
1.5
1.7
2.0
2.7
ns
tPDD
Internal Decode Module Delay
1.6
1.8
2.0
2.4
3.3
ns
Logic Module Predicted Routing Delays2
tRD1
FO = 1 Routing Delay
0.9
1.0
1.2
1.4
2.0
ns
tRD2
FO = 2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD3
FO =3 Routing Delay
1.6
1.8
2.0
2.4
3.4
ns
tRD4
FO = 4 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
tRD5
FO = 8 Routing Delay
3.3
3.7
4.2
4.9
6.9
ns
tRDD
Decode-to-Output Routing Delay
0.3
0.4
0.5
0.7
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.3
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
1.6
1.7
2.0
2.3
3.2
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.3
3.7
4.2
4.9
6.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.4
4.8
5.5
6.4
9.0
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
tWC
Write Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
tRCKHL
Clock HIGH/LOW Time
3.4
3.8
4.3
5.0
7.0
ns
tRCO
Data Valid After Clock HIGH/LOW
3.4
3.8
4.3
5.0
7.0
ns
tADSU
Address/Data Set-Up Time
1.6
1.8
2.0
2.4
3.4
ns
Synchronous SRAM Operations (continued)
tADH
Address/Data Hold Time
0.0
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX09-PQ100ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX09PQ100I 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 14K Gates 336 Cells 129MHz/215MHz 0.45um Technology 3.3V/5V 100-Pin PQFP
A42MX09-PQ100I 功能描述:IC FPGA MX SGL CHIP 14K 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A42MX09-PQ100M 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 14K Gates 336 Cells 129MHz/215MHz 0.45um Technology 3.3V/5V 100-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA 14K GATES 336 CELLS 129MHZ/215MHZ 0.45UM 3.3V/5V 100PQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 14K 100-PQFP
A42MX09-PQ144 功能描述:IC FPGA 144 I/O 160QFP 制造商:microsemi corporation 系列:MX 零件狀態(tài):在售 I/O 數(shù):95 柵極數(shù):14000 電壓 - 電源:3 V ~ 3.6 V，4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C（TA） 標(biāo)準(zhǔn)包裝:1
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