- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379523 > A42MX09-1PQ100I (Electronic Theatre Controls, Inc.) 40MX and 42MX FPGA Families PDF資料下載
參數(shù)資料
| 型號： | A42MX09-1PQ100I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 83/123頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX09-1PQ100I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁當前第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁
40MX and 42MX FPGA Families
v6.0
1-77
Pin Descriptions
CLK/A/B, I/O
Global Clock
Clock inputs for clock distribution networks. CLK is for
40MX while CLKA and CLKB are for 42MX devices. The
clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
DCLK, I/O
Diagnostic Clock
Clock
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
input
for
diagnostic
probe
and
device
GND
Ground
Input LOW supply voltage.
I/O
Input/Output
Input, output, tristate or bi-directional buffer. Input and
output levels are compatible with standard TTL and
CMOS specifications. Unused I/Os pins are configured by
the Designer software as shown in
Table 40
.
In all cases, it is recommended to tie all unused MX I/O
pins to LOW on the board. This applies to all dual-
purpose pins when configured as I/Os as well.
LP
Low Power Mode
Controls the low power mode of all 42MX devices. The
device is placed in the low power mode by connecting
the LP pin to logic HIGH. In low power mode, all I/Os are
tristated, all input buffers are turned OFF, and the core
of the device is turned OFF. To exit the low power mode,
the LP pin must be set LOW. The device enters the low
power mode 800ns after the LP pin is driven to a logic
HIGH. It will resume normal operation in 200μs after the
LP pin is driven to a logic LOW.
MODE
Mode
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). The MODE pin is held HIGH to provide
verification capability. The MODE pin should be
terminated to GND through a 10k
resistor so that the
MODE pin can be pulled HIGH when required.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O
PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-
defined design node within the device. Each diagnostic
pin can be used in conjunction with the other probe pin
to allow real-time diagnostic output of any signal path
within the device. The Probe pin can be used as a user-
defined I/O when verification has been completed. The
pin's probe capabilities can be permanently disabled to
protect programmed design confidentiality. The Probe
pin is accessible when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW.
QCLKA/B/C/D, I/O Quadrant Clock
Quadrant clock inputs for A42MX36 devices. When not
used as a register control signal, these pins can function
as user I/Os.
SDI, I/O
Serial Data Input
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO, I/O
Serial Data Output
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO is available for 42MX devices only.
When Silicon Explorer II is being used, SDO will act as an
output while the "checksum" command is run. It will
return to user I/O when "checksum" is complete.
TCK, I/O
Test Clock
Clock signal to shift the Boundary Scan Test (BST) data
into the device. This pin functions as an I/O when
"Reserve JTAG" is not checked in the Designer Software.
BST pins are only available in A42MX24 and A42MX36
devices.
TDI, I/O
Test Data In
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when "Reserve JTAG" is not checked in the
Designer Software. BST pins are only available in
A42MX24 and A42MX36 devices.
TDO, I/O
Test Data Out
Serial data output for BST instructions and test data. This
pin functions as an I/O when "Reserve JTAG" is not
checked in the Designer Software. BST pins are only
available in A42MX24 and A42MX36 devices.
Table 40
Configuration of Unused I/Os
Device
Configuration
A40MX02, A40MX04
Pulled LOW
A42MX09, A42MX16
Pulled LOW
A42MX24, A42MX36
Tristated
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX09-1PQ100M | 40MX and 42MX FPGA Families |
| A42MX09-1TQ100M | 40MX and 42MX FPGA Families |
| A42MX09-1VQ100I | 40MX and 42MX FPGA Families |
| A42MX09-1VQ100M | 40MX and 42MX FPGA Families |
| A42MX09-2BG100M | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX09-1PQ100M | 制造商:Microsemi Corporation 功能描述:FPGA 14K GATES 336 CELLS 148MHZ/247MHZ 0.45UM 3.3V/5V 100PQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 83 I/O 100PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 14K 100-PQFP |
| A42MX09-1PQ160 | 功能描述:IC FPGA MX SGL CHIP 14K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX09-1PQ160I | 功能描述:IC FPGA MX SGL CHIP 14K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX09-1PQ160M | 制造商:Microsemi Corporation 功能描述:FPGA 14K GATES 336 CELLS 148MHZ/247MHZ 0.45UM 3.3V/5V 160PQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 101 I/O 160PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 14K 160-PQFP |
| A42MX09-1PQG100 | 功能描述:IC FPGA MX SGL CHIP 14K 100-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設(shè)備封裝:256-FPBGA（17x17） |
發(fā)布緊急采購，3分鐘左右您將得到回復。