參數(shù)資料
型號： A42MX09-1BG100M
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 81/123頁
文件大?。?/td> 854K
代理商： A42MX09-1BG100M
40MX and 42MX FPGA Families
v6.0
1-75
Input Module Predicted Routing Delays
2
t
IRD1
t
IRD2
t
IRD3
t
IRD4
t
IRD8
Global Clock Network
FO=1 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
FO=2 Routing Delay
3.2
3.5
4.1
4.8
6.7
ns
FO=3 Routing Delay
3.7
4.1
4.7
5.5
7.7
ns
FO=4 Routing Delay
4.2
4.6
5.3
6.2
8.7
ns
FO=8 Routing Delay
6.1
6.8
7.7
9.0
12.6
ns
t
CKH
Input LOW to HIGH
FO=32
FO=635
4.6
5.0
5.1
5.6
5.7
6.3
6.7
7.4
9.3
10.3
ns
ns
t
CKL
Input HIGH to LOW
FO=32
FO=635
5.3
6.8
5.9
7.6
6.7
8.6
7.8
10.1
11.0
14.1
ns
ns
t
PWH
Minimum Pulse
Width HIGH
FO=32
FO=635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
t
PWL
Minimum Pulse
Width LOW
FO=32
FO=635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
t
CKSW
Maximum Skew
FO=32
FO=635
1.0
1.0
1.2
1.2
1.3
1.3
1.5
1.5
2.2
2.2
ns
ns
t
SUEXT
Input Latch
External Set-Up
FO=32
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
t
HEXT
Input Latch
External Hold
FO=32
FO=635
4.0
4.6
4.4
5.2
5.0
5.9
5.9
6.9
8.2
9.6
ns
ns
t
P
Minimum Period
(1/f
MAX
)
Maximum Datapath
Frequency
FO=32
FO=635
9.2
9.9
10.2
11.0
11.1
12.0
12.7
13.8
21.2
23.0
ns
ns
f
MAX
FO=32
FO=635
108
100
98
91
90
83
79
73
47
44
MHz
MHz
TTL Output Module Timing
5
t
DLH
t
DHL
t
ENZH
t
ENZL
t
ENHZ
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Data-to-Pad HIGH
3.6
4.0
4.5
5.3
7.4
ns
Data-to-Pad LOW
4.2
4.6
5.2
6.2
8.6
ns
Enable Pad Z to HIGH
3.7
4.2
4.7
5.5
7.7
ns
Enable Pad Z to LOW
4.1
4.6
5.2
6.1
8.5
ns
Enable Pad HIGH to Z
7.34
8.2
9.3
10.9
15.3
ns
Table 39
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
CCA
= 3.0V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
相關PDF資料
PDF描述
A42MX09-1CQ100M 40MX and 42MX FPGA Families
A42MX09-1PL100 40MX and 42MX FPGA Families
A42MX09-1PL100A 40MX and 42MX FPGA Families
A42MX09-1PL100B 40MX and 42MX FPGA Families
A42MX09-1PL100ES 40MX and 42MX FPGA Families
相關代理商/技術參數(shù)
參數(shù)描述
A42MX09-1CQ100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX09-1CQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX09-1CQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX09-1CQ100ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX09-1CQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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