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| 型號(hào)： | A42MX04-FCQ100ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 78/123頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX04-FCQ100ES |
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40MX and 42MX FPGA Families
1-72
v6.0
TTL Output Module Timing
5
(Continued)
t
ENLZ
t
GLH
t
GHL
t
LSU
t
LH
t
LCO
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
G-to-Pad HIGH
2.9
3.3
3.7
4.4
6.1
ns
G-to-Pad LOW
2.9
3.3
3.7
4.4
6.1
ns
I/O Latch Output Set-Up
0.5
0.5
0.6
0.7
1.0
ns
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
5.7
6.3
7.1
8.4
11.8
ns
t
ACO
Array Latch Clock-to-Out (Pad-
to-Pad) 32 I/O
7.8
8.6
9.8
11.5
16.1
ns
d
TLH
d
THL
CMOS Output Module Timing
5
Capacitive Loading, LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
Capacitive Loading, HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
t
DLH
t
DHL
t
ENZH
t
ENZL
t
ENHZ
t
ENLZ
t
GLH
t
GHL
t
LSU
t
LH
t
LCO
Data-to-Pad HIGH
3.5
3.9
4.5
5.2
7.3
ns
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
Enable Pad Z to LOW
2.9
3.3
3.7
4.3
6.1
ns
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
G-to-Pad HIGH
5.0
5.6
6.3
7.5
10.4
ns
G-to-Pad LOW
5.0
5.6
6.3
7.5
10.4
ns
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
5.7
6.3
7.1
8.4
11.8
ns
t
ACO
Array Latch Clock-to-Out (Pad-
to-Pad) 32 I/O
7.8
8.6
9.8
11.5
16.1
ns
d
TLH
d
THL
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Capacitive Loading, LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
Capacitive Loading, HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
Table 38
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX04-FCQ100I | 40MX and 42MX FPGA Families |
| A42MX04-FCQ100M | 40MX and 42MX FPGA Families |
| A42MX04-FPL100 | 40MX and 42MX FPGA Families |
| A42MX04-FPL100A | 40MX and 42MX FPGA Families |
| A42MX04-FPL100B | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX04-FCQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-FCQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-FPL100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-FPL100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-FPL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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