
40MX and 42MX FPGA Families
v6.0
1-35
PCI System Timing Specification
Table 26
and
Table 27
list the critical PCI timing
parameters and the corresponding timing parameters
for the MX PCI-compliant devices.
PCI Models
Actel provides synthesizable VHDL and Verilog-HDL
models for a PCI Target interface, a PCI Target and
Target+DMA Master interface. Contact your Actel sales
representative for more details.
Table 26
Clock Specification for 33 MHz PCI
Symbol
Parameter
PCI
A42MX24
A42MX36
Units
Min.
Max.
Min.
Max.
Min.
Max.
t
CYC
CLK Cycle Time
30
–
4.0
–
4.0
–
ns
t
HIGH
CLK High Time
11
–
1.9
–
1.9
–
ns
t
LOW
CLK Low Time
11
–
1.9
–
1.9
–
ns
Table 27
Timing Parameters for 33 MHz PCI
PCI
A42MX24
A42MX36
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
t
VAL
CLK to Signal Valid—Bused Signals
2
11
2.0
9.0
2.0
9.0
ns
t
VAL(PTP)
CLK to Signal Valid—Point-to-Point
2
2
12
2.0
9.0
2.0
9.0
ns
t
ON
Float to Active
2
–
2.0
4.0
2.0
4.0
ns
t
OFF
Active to Float
–
28
–
8.3
1
–
8.3
1
ns
t
SU
Input Set-Up Time to CLK—Bused Signals
7
–
1.5
–
1.5
–
ns
t
SU(PTP)
Input Set-Up Time to CLK—Point-to-Point
10, 12
2
–
1.5
–
1.5
–
ns
t
H
Input Hold to CLK
0
–
0
–
0
–
ns
Notes:
1. T
OFF
is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bussed signals.
GNT# has a setup of 10; REW# has a setup of 12.