參數(shù)資料
型號： A42MX04-2CQ100ES
廠商： Electronic Theatre Controls, Inc.
英文描述： Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:Stripped End Leads; Cable Length:2m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 78/123頁
文件大小： 854K
代理商： A42MX04-2CQ100ES
40MX and 42MX FPGA Families
1- 52
v6.0
Table 33
A42MX09 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Logic Module Propagation Delays1
tPD1
Single Module
1.6
1.8
2.1
2.5
3.5
ns
tCO
Sequential Clock-to-Q
1.8
2.0
2.3
2.7
3.8
ns
tGO
Latch G-to-Q
1.7
1.9
2.1
2.5
3.5
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.0
2.2
2.5
2.9
4.1
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.0
1.1
1.2
1.4
2.0
ns
tRD2
FO=2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD3
FO=3 Routing Delay
1.6
1.8
2.0
2.4
3.3
ns
tRD4
FO=4 Routing Delay
1.9
2.1
2.4
2.9
4.0
ns
tRD8
FO=8 Routing Delay
3.2
3.6
4.1
4.8
6.7
ns
Logic Module Sequential Timing 3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.7
0.8
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.7
5.3
6.0
7.0
9.8
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.2
6.9
7.8
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
5.0
5.6
6.2
7.1
9.9
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.3
0.4
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.3
0.4
0.6
ns
fMAX
Flip-Flop (Latch) Clock
Frequency
161
146
135
117
70
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
PDF描述
A42MX09-2CQ100ES Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:2m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes
A42MX16-2CQ100ES Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:Stripped End Leads; Cable Length:5m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes
A42MX24-2CQ100ES Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:5m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes
A42MX36-2CQ100ES Eurofast Cordset , Eurofast molded cordset RoHS Compliant: Yes
A42MX02-2CQ100I Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:2m; No. of Contacts:3; No. of Positions:4 RoHS Compliant: Yes
相關代理商/技術參數(shù)
參數(shù)描述
A42MX04-2CQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX04-2CQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX04-2PL100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX04-2PL100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX04-2PL100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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