參數(shù)資料
型號： A42MX04-2BG100B
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 101/123頁
文件大?。?/td> 854K
代理商： A42MX04-2BG100B
40MX and 42MX FPGA Families
v6.0
1-73
Table 39
A42MX36 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
1.9
2.1
2.3
2.7
3.8
ns
tPDD
Internal Decode Module Delay
2.2
2.5
2.8
3.3
4.7
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.3
1.5
1.7
2.0
2.7
ns
tRD2
FO=2 Routing Delay
1.8
2.0
2.3
2.7
3.7
ns
tRD3
FO=3 Routing Delay
2.3
2.5
2.8
3.4
4.7
ns
tRD4
FO=4 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tRD5
FO=8 Routing Delay
4.6
5.2
5.8
6.9
9.6
ns
tRDD
Decode-to-Output Routing Delay
0.5
0.6
0.7
1.0
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tGO
Latch Gate-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
2.2
2.4
2.7
3.2
4.5
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.1
6.8
7.7
9.0
12.6
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tWC
Write Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tRCKHL
Clock HIGH/LOW Time
4.8
5.3
6.0
7.0
9.8
ns
tRCO
Data Valid After Clock HIGH/LOW
4.8
5.3
6.0
7.0
9.8
ns
tADSU
Address/Data Set-Up Time
2.3
2.5
2.8
3.4
4.8
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A42MX09-2BG100B 40MX and 42MX FPGA Families
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A42MX36-2BG100B 40MX and 42MX FPGA Families
A42MX02-2BG100ES Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:30mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:30mm; Sensor Housing:Barrel
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX04-2BG100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX04-2BG100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX04-2BG100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX04-2CQ100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX04-2CQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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