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| 型號(hào)： | A42MX04-2BG100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 86/123頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX04-2BG100A |
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40MX and 42MX FPGA Families
v6.0
1-59
Table 35
A42MX16 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
Logic Module Propagation Delays1
tPD1
Single Module
1.9
2.1
2.4
2.8
4.0
ns
tCO
Sequential Clock-to-Q
2.0
2.2
2.5
3.0
4.2
ns
tGO
Latch G-to-Q
1.9
2.1
2.4
2.8
4.0
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.2
2.4
2.8
3.3
4.6
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.1
1.2
1.4
1.6
2.3
ns
tRD2
FO=2 Routing Delay
1.5
1.6
1.8
2.1
3.0
ns
tRD3
FO=3 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
tRD4
FO=4 Routing Delay
2.2
2.4
2.7
3.2
4.5
ns
tRD8
FO=8 Routing Delay
3.6
4.0
4.5
5.3
7.5
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.8
5.3
6.0
7.1
9.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.2
6.9
7.9
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
9.5
10.6
12.0
14.1
19.8
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.7
0.8
0.9
1.01
1.4
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.7
0.8
0.89
1.01
1.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
129
117
108
94
56
MHz
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX09-2BG100A | Inductive Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:20mm; Sensor Output:AC/DC; Switch Terminals:Cable; Load Current Max:400mA; Sensing Face Diameter:30mm; Sensor Connection:2 m Cable; Sensor Housing:Barrel RoHS Compliant: Yes |
| A42MX16-2BG100A | 40MX and 42MX FPGA Families |
| A42MX24-2BG100A | 40MX and 42MX FPGA Families |
| A42MX36-2BG100A | 40MX and 42MX FPGA Families |
| A42MX02-2BG100B | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX04-2BG100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-2BG100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-2BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-2BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-2CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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