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| 型號(hào)： | A42MX04-1BG100I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 79/123頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX04-1BG100I |
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40MX and 42MX FPGA Families
v6.0
1-53
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.8
2.17
3.0
ns
tINYL
Pad-to-Y LOW
1.2
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
1.8
2.0
2.3
2.7
3.7
ns
tINGL
G to Y LOW
1.8
2.0
2.3
2.7
3.7
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
2.8
3.2
3.6
4.2
5.9
ns
tIRD2
FO=2 Routing Delay
3.2
3.5
4.0
4.7
6.6
ns
tIRD3
FO=3 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD4
FO=4 Routing Delay
3.9
4.3
4.9
5.7
8.0
ns
tIRD8
FO=8 Routing Delay
5.2
5.8
6.6
7.7
10.8
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
4.1
4.5
5.0
5.1
5.6
6.0
6.7
8.4
9.3
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
5.0
5.4
5.5
6.0
6.2
6.8
7.3
8.0
10.2
11.2
ns
tPWH
Minimum
Pulse
Width HIGH
FO = 32
FO = 256
1.7
1.9
2.1
2.3
2.5
2.7
3.5
3.8
ns
tPWL
Minimum
Pulse
Width LOW
FO = 32
FO = 256
1.7
1.9
2.1
2.3
2.5
2.7
3.5
3.8
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
0.4
0.5
0.6
0.9
ns
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 256
0.0
ns
tHEXT
Input Latch External
Hold
FO = 32
FO = 256
3.3
3.7
4.1
4.2
4.6
4.9
5.5
6.9
7.6
ns
tP
Minimum Period
FO = 32
FO = 256
5.6
6.1
6.2
6.8
6.7
7.4
7.8
8.5
12.9
14.2
ns
fMAX
Maximum
Frequency
FO = 32
FO = 256
177
161
146
148
135
129
117
77
70
MHz
Table 33
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX04-1BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-1CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-1CQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-1CQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX04-1CQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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