參數(shù)資料
型號： A42MX02-1CQ100
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 18/53頁
文件大?。?/td> 854K
代理商： A42MX02-1CQ100
40MX and 42MX FPGA Families
v6.0
1-19
Output Drive Characteristics for 5.0V PCI Signaling
MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 1-16 on page 1-21 shows
the typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local Bus
Specification.
Table 17
DC Specification (5.0V PCI Signaling)1
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
VCCI
Supply Voltage for I/Os
4.75
5.25
4.75
5.252
V
VIH
Input High Voltage
2.0
VCC + 0.5
2.0
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
VIN = 2.7V
70
—
10
A
IIL
Input Low Leakage Current
VIN=0.5V
–70
—
–10
A
VOH
Output High Voltage
IOUT = –2 mA
IOUT = –6 mA
2.4
3.84
V
VOL
Output Low Voltage
IOUT = 3 mA,
6 mA
0.55
—
0.33
V
CIN
Input Pin Capacitance
10
—
10
pF
CCLK
CLK Pin Capacitance
5
12
—
10
pF
LPIN
Pin Inductance
20
—
< 8 nH3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.
2. Maximum rating for VCCI –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
Table 18
AC Specifications (5.0V PCI Signaling)*
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
ICL
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN +1)
/0.015
–60
–10
mA
Slew (r)
Output Rise Slew Rate
0.4V to 2.4V load
1
5
1.8
2.8
V/ns
Slew (f)
Output Fall Slew Rate
2.4V to 0.4V load
1
5
2.8
4.3
V/ns
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.
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A42MX02-1CQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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