參數(shù)資料
型號(hào)： A40MX04-PL84M
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場可編程門陣列（FPGA）
文件頁數(shù)： 8/116頁
文件大?。?/td> 3110K
代理商： A40MX04-PL84M
40MX and 42MX FPGA Families
8
v5.0
MultiPlex I/O Modules
MultiPlex I/O supports the most common voltage standards
today: pure 5.0V operation, pure 3.3V operation, and mixed
3.3V operation with 5.0V I/O tolerance for maximum
performance. Internal array performance is retained in 3.3V
systems by using complimentary pass gates that operate as
fast as they do at 5.0V at 3.3V.
MultiPlex I/O includes selectable PCI output drives in
certain 42MX devices, enabling 100% PCI-compliance for
both 5.0V and 3.3V systems. For low-power systems,
MultiPlex I/O is used to turn off all inputs and outputs to cut
current consumption to below 100μA.
The MultiPlex I/O modules provide the interface between
the device pins and the logic array. The top of
Figure 6
is a
block diagram of the 42MX I/O module. A variety of user
functions, determined by a library macro selection, can be
implemented in the module. (Refer to the
Macro Library
Guide
for more information.) All 42MX I/O modules contain
tristate buffers, with input and output latches that can be
configured for input, output, or bi-directional operation.
All 42MX devices contain flexible I/O structures (
Figure 7 on
page 9
), where each output pin has a dedicated
output-enable control. The I/O module can be used to latch
input or output data, or both, providing a fast set-up time. In
addition, the Actel Designer Series software tools can build
a D-type flip-flop using a C-module to register input and
output signals. To achieve 5.0V or 3.3V PCI-compliant output
drives on A42MX24 and A42MX36 devices, a chip-wide PCI
fuse is programmed. When the PCI fuse is not programmed,
the output drive is standard. (See the bottom portion of
Figure 6
.)
Actel
’
s Designer Series development tools provide a design
library of I/O macrofunctions that can implement all I/O
configurations supported by the MX FPGAs.
Routing Structure
The MX architecture uses vertical and horizontal routing
tracks to interconnect the various logic and I/O modules.
These routing tracks are metal interconnects that may be
either of continuous length or broken into pieces called
segments. Varying segment lengths allows the interconnect
of over 90% of design tracks to occur with only two antifuse
connections. Segments can be joined together at the ends
using antifuses to increase their lengths up to the full length
of the track. All interconnects can be accomplished with a
maximum of four antifuses.
Horizontal Routing
Horizontal channels are located between the rows of
modules and are composed of several routing tracks. The
horizontal routing tracks within the channel are divided
into one or more segments. The minimum horizontal
segment length is the width of a module pair, and the
maximum horizontal segment length is the full length of the
channel. Any segment that spans more than one-third at the
row length is considered a long horizontal segment. A
typical channel is shown in
Figure 8 on page 9
.
Non-dedicated horizontal routing tracks are used to route
signal nets; dedicated routing tracks are used for global
clock networks and for power and ground tie-off tracks.
Vertical Routing
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks: input,
output, and long, which are also divided into one or more
segments. Each segment in an input track is dedicated to
the input of a particular module; each segment in an output
track is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
Figure 6
42MX I/O Module
G/CLK*
Q
D
EN
PAD
* Can be Configured as a Latch or D Flip-Flop
(Using C-Module)
From Array
To Array
G/CLK*
Q
D
Signal
PCI Enable
Fuse
PCI
Drive
Schematic
STD
Output
相關(guān)PDF資料
PDF描述
A40MX04-PQ100 Field Programmable Gate Array (FPGA)
A40MX04-PQ100I Field Programmable Gate Array (FPGA)
A40MX04-PQ100M Field Programmable Gate Array (FPGA)
A40MX04-VQ80 Field Programmable Gate Array (FPGA)
A40MX04-VQ80I Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX04-PLG44 功能描述:IC FPGA 69I/O 44PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計(jì):226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28）
A40MX04-PLG44I 功能描述:IC FPGA MX SGL CHIP 6K 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX04-PLG44M 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 44PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 34 I/O 44PLCC
A40MX04-PLG68 功能描述:IC FPGA 69I/O 68PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計(jì):226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28）
A40MX04-PLG68I 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
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