參數(shù)資料
型號: A40MX04-PL84I
廠商: Microsemi SoC
文件頁數(shù): 63/142頁
文件大?。?/td> 0K
描述: IC FPGA MX SGL CHIP 6K 84-PLCC
標準包裝: 16
系列: MX
輸入/輸出數(shù): 69
門數(shù): 6000
電源電壓: 3 V ~ 3.6 V,4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 84-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 84-PLCC(29.31x29.31)
40MX and 42MX FPGA Families
Re vi s i on 11
1 - 23
Output Drive Characteristics for 5.0 V PCI Signaling
MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 1-15 on
page 1-25 shows the typical output drive characteristics of the MX devices. MX output drivers are
compliant with the PCI Local Bus Specification.
Table 1-17 DC Specification (5.0 V PCI Signaling)1
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
VCCI
Supply Voltage for I/Os
4.75
5.25
4.75
5.252
V
VIH
Input High Voltage
2.0
VCC + 0.5
2.0
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
VIN = 2.7 V
70
10
A
IIL
Input Low Leakage Current
VIN=0.5 V
–70
–10
A
VOH
Output High Voltage
IOUT = –2 mA
IOUT = –6 mA
2.4
3.84
V
VOL
Output Low Voltage
IOUT = 3 mA, 6 mA
0.55
0.33
V
CIN
Input Pin Capacitance
10
10
pF
CCLK
CLK Pin Capacitance
5
12
10
pF
LPIN
Pin Inductance
20
< 8 nH3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.
2. Maximum rating for VCCI –0.5 V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and
capacitance.
Table 1-18 AC Specifications (5.0V PCI Signaling)*
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
ICL
Low Clamp Current
–5 < VIN
–1
–25 + (VIN +1) /0.015
–60
–10
mA
Slew (r)
Output Rise Slew Rate
0.4 V to 2.4 V load
1
5
1.8
2.8
V/ns
Slew (f)
Output Fall Slew Rate
2.4 V to 0.4 V load
1
5
2.8
4.3
V/ns
Note:
*PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.
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