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參數(shù)資料
| 型號： | A40MX04-PL68I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 9/116頁 |
| 文件大?。?/td> | 3110K |
| 代理商： | A40MX04-PL68I |
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v5.0
9
40MX and 42MX FPGA Families
routing. Each output segment spans four channels (two
above and two below), except near the top and bottom of
the array, where edge effects occur. Long vertical tracks
contain either one or two segments. An example of vertical
routing tracks and segments is shown in
Figure 8
.
Antifuse Structures
An antifuse is a
“
normally open
”
structure as opposed to the
normally connected fuse structure used in PROMs or PALs.
The use of antifuses to implement a programmable logic
device results in highly testable structures as well as
efficient programming algorithms. The structure is
highly-testable because there are no pre-existing
connections; therefore, temporary connections can be made
using pass transistors. These temporary connections can
isolate individual antifuses to be programmed and
individual circuit structures to be tested, which can be done
before and after programming. For example, all metal
tracks can be tested for continuity and shorts between
adjacent tracks, and the functionality of all logic modules
can be verified.
Clock Networks
The 40MX devices have one global clock distribution
network (CLK). Two low-skew, high-fanout clock
distribution networks are provided in each 42MX device.
These networks are referred to as
CLK0
and
CLK1
. Each
network has a clock module (CLKMOD) that selects the
source of the clock signal and may be driven as follows:
Externally from the CLKA pad
Externally from the CLKB pad
Internally from the CLKINTA input
Internally from the CLKINTB input
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
The user controls the clock module by selecting one of two
clock macros from the macro library. The macro CLKBUF is
used to connect one of the two external clock pins to a clock
network, and the macro CLKINT is used to connect an
internally-generated clock signal to a clock network. Since
both clock networks are identical, it does not matter
whether CLK0 or CLK1 is being used. The clock input pads
can also be used as normal I/Os, bypassing the clock
networks (
Figure 9
).
The A42MX36 device has four additional register control
resources, called quadrant clock networks (
Figure 10 on
page 10
). Each quadrant clock provides a local, high-fanout
resource to the contiguous logic modules within its
quadrant of the device. Quadrant clock signals can originate
from specific I/O pins or from the internal array and can be
used as a secondary register clock, register clear, or output
enable.
Figure 7
40MX I/O Module
OE
From Internal Logic
To Internal Logic
Figure 8
Routing Structure
Figure 9
Clock Networks
Vertical Routing Tracks
Antifuses
Logic
Modules
Segmented
Horizontal
Routing
Tracks
CLKB
CLKA
From
Pads
Clock
Drivers
CLKMOD
CLKINB
CLKINA
S0
S1
Internal
Signal
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Clock Tracks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A40MX04-PL68M | Field Programmable Gate Array (FPGA) |
| A42MX09-1PQ160I | Field Programmable Gate Array (FPGA) |
| A42MX09-1PQ160M | Field Programmable Gate Array (FPGA) |
| A42MX09-1TQ176 | Field Programmable Gate Array (FPGA) |
| A42MX09-1TQ176I | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A40MX04-PL68M | 制造商:Microsemi Corporation 功能描述:FPGA 40MX Family 6K Gates 547 Cells 83MHz/139MHz 0.45um Technology 3.3V/5V 68-Pin PLCC 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 68PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 57 I/O 68PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC |
| A40MX04-PL68X4 | 制造商:Microsemi Corporation 功能描述:MX SERIES 6000 GATES FPGA |
| A40MX04-PL84 | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-PL84A | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-PL84I | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
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