參數(shù)資料
型號: A40MX04-PL68
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 6/116頁
文件大?。?/td> 3110K
代理商: A40MX04-PL68
40MX and 42MX FPGA Families
6
v5.0
The 42MX devices contain three types of logic modules:
combinatorial (C-modules), sequential (S-modules), and
decode (D-modules).
The C-module, shown in
Figure 2
, implements the following
function:
Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11
where
S0=A0*B0
S1=A1+B1
The S-module, shown in
Figure 3
, is designed to implement
high-speed sequential functions within a single logic
module. The S-module implements the same combinatorial
logic function as the C-module while adding a sequential
element. The sequential element can be configured as
either a D flip-flop or a transparent latch. To increase
flexibility, the S-module register can be bypassed so that it
implements purely combinatorial logic.
Figure 2
C-Module Implementation
D00
D01
D10
D11
S0
S1
Y
A0
B0
A1
B1
Figure 3
S-Module Implementation
D11
S1
D01
D00
D10
Y
OUT
S0
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D11
S1
D01
D00
D10
Y
S0
Up to 7-Input Function Plus Latch
Y
Up to 4-Input Function Plus Latch with Clear
D11
S1
D01
D00
D10
Y
OUT
S0
Up to 8-Input Function Same as C-Module)
S
D1
D0
CLR
D
Q
OUT
CLR
D
Q
OUT
GATE
D
Q
GATE
相關(guān)PDF資料
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