參數(shù)資料
型號: A40MX04-PL44M
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 12/116頁
文件大?。?/td> 3110K
代理商: A40MX04-PL44M
40MX and 42MX FPGA Families
12
v5.0
Table 2
BST Instructions
Test Mode
Code
Description
EXTEST
000
Allows the external circuitry and
board-level interconnections to
be tested by forcing a test
pattern at the output pins and
capturing test results at the
input pins.
SAMPLE/
PRELOAD
001
Allows a snapshot of the signals
at the device pins to be
captured and examined during
device operation.
JPROBE
011
A private instruction allowing the
user to connect Actel
s Micro
Probe registers to the test
chain.
USER
INSTRUCTION
100
Allows the user to build
application-specific instructions
such as RAM READ and RAM
WRITE.
HIGH Z
101
Refer to the IEEE Standard
1149.1 specification.
CLAMP
110
Refer to the IEEE Standard
1149.1 specification.
BYPASS
111
Enables the bypass register
between the TDI and TDO pins.
The test data passes through
the selected device to adjacent
devices in the test chain.
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