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| 型號： | A40MX04-3PQ100I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 30/116頁 |
| 文件大小： | 3110K |
| 代理商： | A40MX04-3PQ100I |
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40MX and 42MX FPGA Families
30
v5.0
Predictable Performance:
Tight Delay Distributions
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of
inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer routing tracks.
The MX FPGAs deliver a tight fanout delay distribution,
which is achieved in two ways: by decreasing the delay of the
interconnect elements and by decreasing the number of
interconnect elements per path.
Actel
’
s
patented
antifuse
resistive/capacitive interconnect. The antifuses, fabricated
in 0.45 μ lithography, offer nominal levels of 100
resistance and 7.0 femtofarad (fF) capacitance per antifuse.
MX fanout distribution is also tight due to the low number of
antifuses required for each interconnect path. The
proprietary architecture limits the number of antifuses per
path to a maximum of four, with 90 percent of interconnects
using only two antifuses.
offers
a
very
low
Timing Characteristics
Device timing characteristics fall into three categories:
family-dependent, device-dependent, and design-dependent.
The input and output buffer characteristics are common to
all MX devices. For mixed voltage of the A42MX devices, the
timing numbers are defined in the 3.3V section for I/Os while
for the internal logic resources, the timing numbers are
defined in the 5.0V section. Internal routing delays are
device-dependent. Design dependency means actual delays
are not determined until after place-and-route of the user
’
s
design is complete. Delay values may then be determined by
using the Designer Series utility or by performing simulation
with post-layout delays.
Critical Nets and Typical Nets
Propagation delays in this data sheet apply to typical nets.
The abundant routing resources in the MX architecture
allows for deterministic timing using Actel
’
s Designer Series
development tools, which include TDPR, a timing-driven
place-and-route tool. Using Timer, the designer can specify
timing-critical nets and system clock frequency. Using these
timing specifications, the place-and-route software
optimizes the layout of the design to meet the user
’
s
specifications.
Long Tracks
Some nets in the design use long tracks, which are special
routing resources that span multiple rows, columns, or
modules. Long tracks employ three and sometimes four
antifuse connections, which increase capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6 percent of
nets in a fully utilized device require long tracks. Long
tracks add approximately a 3 ns to a 6 ns delay, which is
represented statistically in higher fanout (FO=8) routing
delays in the data sheet specifications section, beginning on
page 34
.
Timing Derating
A timing derating factor of 0.45 is used to reflect best-case
processing. Note that this factor is relative to the standard
speed timing parameters and must be multiplied by the
appropriate voltage and temperature derating factors for a
given application.
Timing Derating Factors
Commercial to Industrial
Commercial Worst-Case to Typical
Industrial
Min.
Max.
(Commercial Specification) x
0.69
1.11
Commerical Typical
(T
J
= 25
°
C, V
CC
= 5.0V)
(Commercial, Worst-Case
Condition) x
0.85
Note:
This derating factor applies to all routing and propagation
delays.
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| A40MX04-3VQ80I | Field Programmable Gate Array (FPGA) |
| A40MX04-3VQ80M | Field Programmable Gate Array (FPGA) |
| A40MX04-FPL44 | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A40MX04-3PQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A40MX04-3PQG100 | 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-3PQG100I | 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-3VQ80 | 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-3VQ80I | 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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