參數(shù)資料
型號: A40MX04-2PL68M
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 15/116頁
文件大?。?/td> 3110K
代理商: A40MX04-2PL68M
v5.0
15
40MX and 42MX FPGA Families
Output Drive Characteristics for
5.0V PCI Signaling
MX PCI device I/O drivers were designed specifically for
high-performance PCI systems.
Figure 12 on page 17
shows
the typical output drive characteristics of the MX devices.
MX output drivers are compliant with the PCI Local Bus
Specification.
DC Specification (5.0V PCI Signaling)
1
PCI
MX
Symbol
Parameter
Condition
Minimum
Maximum
Minimum
Maximum
Units
V
CC
V
IH
V
IL
I
IH
I
IL
Supply Voltage
4.75
5.25
4.75
5.25
2
V
Input High Voltage
2.0
V
CC
+ 0.5
0.8
2.0
V
CC
+ 0.3
0.8
V
Input Low Voltage
0.5
0.3
V
Input High Leakage Current
V
IN
= 2.7
V
IN
=0.5
I
OUT
=
2 mA
I
OUT
=
6 mA
I
OUT
= 3 mA,
6 mA
70
10
μA
Input Low Leakage Current
70
10
μA
V
OH
Output High Voltage
2.4
3.84
V
V
OL
Output Low Voltage
0.55
0.33
V
C
IN
C
CLK
L
PIN
Notes:
1.
2.
3.
Input Pin Capacitance
10
10
pF
CLK Pin Capacitance
5
12
10
pF
Pin Inductance
20
< 8 nH
3
nH
PCI Local Bus Specification Section 4.2.1.1.
Maximum rating for V
CC
0.5V to 7.0V.
Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
AC Specifications (5.0V PCI Signaling)
1
PCI
MX
Symbol
Parameter
Condition
Minimum
Maximum
Minimum
Maximum
Units
I
CL
Low Clamp Current
5 < V
IN
1
25 + (V
IN
+1)
/0.015
60
10
mA
Slew (r)
Output Rise Slew Rate
0.4V to 2.4V load
1
5
1.8
2.8
V/ns
Slew (f)
Output Fall Slew Rate
2.4V to 0.4V load
1
5
2.8
4.3
V/ns
Note:
1.
PCI Local Bus Specification Section 4.2.1.2.
相關(guān)PDF資料
PDF描述
A40MX04-2PL84 Field Programmable Gate Array (FPGA)
A40MX04-2PL84I Field Programmable Gate Array (FPGA)
A40MX04-2PL84M Field Programmable Gate Array (FPGA)
A40MX04-2PQ100 Field Programmable Gate Array (FPGA)
A40MX04-2PQ100I Field Programmable Gate Array (FPGA)
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