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參數(shù)資料
| 型號(hào)： | A40MX04-2PL68 |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁(yè)數(shù)： | 11/116頁(yè) |
| 文件大小： | 3110K |
| 代理商： | A40MX04-2PL68 |
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v5.0
11
40MX and 42MX FPGA Families
When a device is operating in BST mode, four I/O pins are
used for the TDI, TDO, TMS, and TCK signals. An active
reset (nTRST) pin is not supported; however, the 42MX
device contain power-on circuitry that resets the boundary
scan circuitry upon power-up.
Table 1
summarizes the
functions of the IEEE 1149.1 BST signals.
JTAG
All SX-A devices are IEEE 1149.1 (JTAG) compliant. SX-A
devices offer superior diagnostic and testing capabilities by
providing JTAG and probing capabilites. These functions
are controlled through the special JTAG pins in conjunction
with the program fuse.
JTAG fuse programmed:
TCK must be terminated
—
logical high or low doesn
’
t
matter (to avoid floating input)
TDI, TMS may float or at logical high (internal pull-up is
present)
TDO may float or connect to TDI of another device (it
’
s an
output)
JTAG fuse not programmed:
TCK, TDI, TDO, TMS are user I/O. If not used, they will be
configured as tristated output.
BST Instructions
Boundary scan testing within the 42MX devices is controlled
by a Test Access Port (TAP) state machine. The TAP
controller drives the three-bit instruction register, a bypass
register, and the boundary scan data registers within the
device. The TAP controller uses the TMS signal to control
the testing of the device. The BST mode is determined by
the bitstream entered on the TMS pin.
Table 2
describes the
test instructions supported by the 42MX devices.
Reset
The TMS pin is equipped with an internal pull-up resistor.
This allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
Figure 11
42MX IEEE 1149.1 Boundary Scan Circuitry
JPROBE Register
Boundary Scan Register
Instruction
Decode
Control Logic
TAP Controller
Instruction
Register
Bypass
Register
TMS
TCK
TDI
Output
MUX
TDO
JTAG
JTAG
Table 1
IEEE 1149.1 BST Signals
Signal
Name
Function
TDI
Test Data In
Serial data input for BST
instructions and data. Data is
shifted in on the rising edge of
TCK.
TDO
Test Data
Out
Serial data output for BST
instructions and test data.
TMS
Test Mode
Select
Serial data input for BST mode.
Data is shifted in on the rising
edge of TCK.
TCK
Test Clock
Clock signal to shift the BST
data into the device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A40MX04-2PL68I | 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-2PL68M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A40MX04-2PL84 | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-2PL84I | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-2PL84M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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