參數(shù)資料
型號： A40MX02-PQG100I
廠商： Microsemi SoC
文件頁數(shù)： 121/142頁
文件大?。?/td> 0K
描述： IC FPGA MX SGL CHIP 3K 100-PQFP
標準包裝： 66
系列： MX
輸入/輸出數(shù)： 57
門數(shù)： 3000
電源電壓： 3 V ~ 3.6 V，4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-PQFP（14x20）
40MX and 42MX FPGA Families
1- 4
R ev isio n 1 1
provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can
be used to implement registers for other user logic within the design.
Routing Structure
The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O
modules. These routing tracks are metal interconnects that may be continuous or split into segments.
Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two
antifuse connections. Segments can be joined together at the ends using antifuses to increase their
lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four
antifuses.
Horizontal Routing
Horizontal routing tracks span the whole row length or are divided into multiple segments and are located
in between the rows of modules. Any segment that spans more than one-third of the row length is
considered a long horizontal segment. A typical channel is shown in Figure 1-6. Within horizontal routing,
dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Non-
dedicated tracks are used for signal nets.
Vertical Routing
Another set of routing tracks run vertically through the module. There are three types of vertical tracks:
input, output, and long. Long tracks span the column length of the module, and can be divided into
multiple segments. Each segment in an input track is dedicated to the input of a particular module; each
segment in an output track is dedicated to the output of a particular module. Long segments are
Figure 1-4
A42MX24 and A42MX36 D-Module Implementation
Figure 1-5
A42MX36 Dual-Port SRAM Block
7 Inputs
Hard-Wire to I/O
Feedback to Array
Programmable
Inverter
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
Read
Port
Logic
Write
Port
Logic
RD[7:0]
Routing Tracks
Latches
Read
Logic
[5:0]
RDAD[5:0]
REN
RCLK
Latches
WD[7:0]
Latches
WRAD[5:0]
Write
Logic
MODE
BLKEN
WEN
WCLK
[5:0]
[7:0]
相關(guān)PDF資料
PDF描述
A40MX02-1PQ100 IC FPGA MX SGL CHIP 3K 100-PQFP
A40MX02-PQ100I IC FPGA MX SGL CHIP 3K 100-PQFP
A54SX08A-PQ208 IC FPGA SX 12K GATES 208-PQFP
EP4CE10F17I8L IC CYCLONE IV FPGA 10K 256FBGA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX02-PQG100M 制造商:Microsemi Corporation 功能描述:FPGA 3K GATES 295 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 100PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 3K 100-PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 57 I/O 100PQFP
A40MX02-TQ208A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX Automotive FPGA Families
A40MX02-VQ208A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX Automotive FPGA Families
A40MX02-VQ80 功能描述:IC FPGA MX SGL CHIP 3K 80-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX02-VQ80A 功能描述:IC FPGA MX SGL CHIP 3K 80-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
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