參數(shù)資料
型號: A40MX02-2PLG68I
廠商: Microsemi SoC
文件頁數(shù): 81/142頁
文件大?。?/td> 0K
描述: IC FPGA MX SGL CHIP 3K 68-PLCC
標準包裝: 19
系列: MX
輸入/輸出數(shù): 57
門數(shù): 3000
電源電壓: 3 V ~ 3.6 V,4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24.23x24.23)
40MX and 42MX FPGA Families
Re vi s i on 11
1 - 39
PCI System Timing Specification
Table 1-26 and Table 1-27 list the critical PCI timing parameters and the corresponding timing
parameters for the MX PCI-compliant devices.
PCI Models
Microsemi provides synthesizable VHDL and Verilog-HDL models for a PCI Target interface, a PCI
Target and Target+DMA Master interface. Contact your Microsemi sales representative for more
details.
Table 1-26 Clock Specification for 33 MHz PCI
Symbol
Parameter
PCI
A42MX24
A42MX36
Units
Min.
Max.
Min.
Max.
Min.
Max.
tCYC
CLK Cycle Time
30
–4.0–4.0
ns
tHIGH
CLK High Time
11
–1.9–1.9
ns
tLOW
CLK Low Time
11
–1.9–1.9
ns
Table 1-27 Timing Parameters for 33 MHz PCI
PCI
A42MX24
A42MX36
Symbol
Parameter
Min.
Max. Min. Max. Min. Max. Units
tVAL
CLK to Signal Valid—Bused Signals
2
11
2.0
9.0
2.0
9.0
ns
tVAL(PTP) CLK to Signal Valid—Point-to-Point
2 2
12
2.0
9.0
2.0
9.0
ns
tON
Float to Active
2
2.0
4.0
2.0
4.0
ns
tOFF
Active to Float
28
8.31
–8.31
ns
tSU
Input Set-Up Time to CLK—Bused Signals
7
1.5
1.5
ns
tSU(PTP) Input Set-Up Time to CLK—Point-to-Point
10, 122
1.5
1.5
ns
tH
Input Hold to CLK
0
0
0
ns
Notes:
1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional
10 ns.
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times
than do bussed signals. GNT# has a setup of 10; REW# has a setup of 12.
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