The MX family of FPGAs is fully supported by Libero
參數(shù)資料
型號(hào)： A40MX02-1PQ100
廠商： Microsemi SoC
文件頁數(shù)： 56/142頁
文件大小： 0K
描述： IC FPGA MX SGL CHIP 3K 100-PQFP
標(biāo)準(zhǔn)包裝： 66
系列： MX
輸入/輸出數(shù)： 57
門數(shù)： 3000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-PQFP（14x20）
40MX and 42MX FPGA Families
1- 16
R e v i sio n 1 1
Development Tool Support
The MX family of FPGAs is fully supported by Libero Integrated Design Environment (IDE). Libero IDE
is a design management environment, seamlessly integrating design tools while guiding the user through
the design flow, managing all design and log files, and passing necessary design data among tools.
Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the
entire design in a single environment. Libero IDE includes SynplifyPro from Synopsys, ModelSim HDL
Simulator from Mentor Graphics, and Viewdraw.
Libero IDE includes place-and-route and provides a comprehensive suite of backend support tools for
FPGA development, including timing-driven place-and-route, and a world-class integrated static timing
analyzer and constraints editor.
Additionally, the back-annotation flow is compatible with all the major simulators and the simulation
results can be cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis
tool. Another tool included in the Libero software is the SmartGen macro builder, which easily creates
popular and commonly used logic functions for implementation into your schematic or HDL design.
Microsemi’s Libero software is compatible with the most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synopsys, and Cadence Design Systems.
Refer to the Libero IDE web content at www.microsemi.com/soc/products/software/libero/default.aspx for
further information on licensing and current operating system support.
Related Documents
Application Notes
User’s Guides and Manuals
Miscellaneous
5.0 V Operating Conditions
Table 1-6
Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
Limits
Units
VCC
DC Supply Voltage
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCC+0.5
V
VO
Output Voltage
–0.5 to VCC+0.5
V
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX02-1PQ100ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A40MX02-1PQ100I 功能描述:IC FPGA MX SGL CHIP 3K 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX02-1PQ100M 制造商:Microsemi Corporation 功能描述:FPGA 40MX Family 3K Gates 295 Cells 96MHz/160MHz 0.45um Technology 3.3V/5V 100-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA 3K GATES 295 CELLS 96MHZ/160MHZ 0.45UM 3.3V/5V 100PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 3K 100-PQFP
A40MX02-1PQG100 功能描述:IC FPGA MX SGL CHIP 3K 100-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX02-1PQG100I 功能描述:IC FPGA MX SGL CHIP 3K 100-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
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