Revision 11 1-5 VersaTiles The ProASIC3 nano core consists of VersaTiles, which have been enhanc" />
參數(shù)資料
型號: A3PN250-ZVQ100
廠商: Microsemi SoC
文件頁數(shù): 13/114頁
文件大小: 0K
描述: IC FPGA NANO 250K GATES 100-VQFP
標(biāo)準(zhǔn)包裝: 90
系列: ProASIC3 nano
RAM 位總計: 36864
輸入/輸出數(shù): 68
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
ProASIC3 nano Flash FPGAs
Revision 11
1-5
VersaTiles
The ProASIC3 nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS
core tiles. The ProASIC3 nano VersaTile supports the following:
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-5 for VersaTile configurations.
User Nonvolatile FlashROM
ProASIC3 nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM
can be used in diverse system applications:
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard ProASIC3 nano IEEE 1532 JTAG programming interface.
The core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in the A3PN030 and smaller devices), as in
security keys stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The ProASIC3 nano development software solutions, Libero System-on-Chip (SoC) software and
Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential
programming files for applications requiring a unique serial number in each part. Another feature enables
the inclusion of static data for system version control. Data for the FlashROM can be generated quickly
and easily using Libero SoC and Designer software tools. Comprehensive programming file support is
also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
Figure 1-5 VersaTile Configurations
X1
Y
X2
X3
LUT-3
Data
Y
CLK
Enable
CLR
D-FF
Data
Y
CLK
CLR
D-FF
LUT-3 Equivalent
D-Flip-Flop with Clear or Set
Enable D-Flip-Flop with Clear or Set
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