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參數(shù)資料
| 型號(hào)： | A3PN060-Z1VQ100 |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 82/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA NANO 60K GATES 100-VQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ProASIC3 nano |
| RAM 位總計(jì)： | 18432 |
| 輸入/輸出數(shù)： | 71 |
| 門數(shù)： | 60000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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Revision 11
1-1
1 – ProASIC3 nano Device Overview
General Description
ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and
features beyond those of the ProASICPLUS family. Nonvolatile flash technology gives ProASIC3 nano
devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3
nano devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These
features enable designers to create high-density systems using existing ASIC or FPGA design flows and
tools.
ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and smaller
devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system gates,
supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.
ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features and
packages for greater customer value in high volume consumer, portable, and battery-backed markets.
Added features include smaller footprint packages designed with two-layer PCBs in mind, low power,
hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-sensitive applications.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based ProASIC3 nano devices allow all functionality to be Instant On; no external
boot PROM is required. On-board security mechanisms prevent access to all the programming
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote
in-system reprogramming to support future design iterations and field upgrades with confidence that
valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using
the industry-standard AES algorithm. The ProASIC3 nano device architecture mitigates the need for
ASIC migration at higher user volumes. This makes the ProASIC3 nano device a cost-effective ASIC
replacement solution, especially for applications in the consumer, networking/communications,
computing, and avionics markets.
With a variety of devices under $1, ProASIC3 nano FPGAs enable cost-effective implementation of
programmable logic and quick time to market.
Security
Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. ProASIC3 nano devices incorporate FlashLock, which
provides a unique combination of reprogrammability and design security without external overhead,
advantages that only an FPGA with nonvolatile flash programming can offer.
ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest
level of protection in the FPGA industry for programmed intellectual property and configuration data. In
addition, all FlashROM data in ProASIC3 nano devices can be encrypted prior to loading, using the
industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was
adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977
DES standard. ProASIC3 nano devices have a built-in AES decryption engine and a flash-based AES
key that make them the most comprehensive programmable logic device security solution available
today. ProASIC3 nano devices with AES-based security provide a high level of protection for remote field
updates over public networks such as the Internet, and are designed to ensure that valuable IP remains
out of the hands of system overbuilders, system cloners, and IP thieves.
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| A3PN060-Z1VQ100I | 功能描述:IC FPGA NANO 60K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| A3PN060-Z1VQG100 | 功能描述:IC FPGA NANO 60K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| A3PN060-Z1VQG100I | 功能描述:IC FPGA NANO 60K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| A3PN060-Z2VQ100 | 功能描述:IC FPGA NANO 60K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| A3PN060-Z2VQ100I | 功能描述:IC FPGA NANO 60K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
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