Revision 11 2-33 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used fo" />
參數(shù)資料
型號: A3PN030-Z1QNG68
廠商: Microsemi SoC
文件頁數(shù): 57/114頁
文件大小: 0K
描述: IC FPGA NANO 30K GATES 68-QFN
標(biāo)準(zhǔn)包裝: 260
系列: ProASIC3 nano
輸入/輸出數(shù): 49
門數(shù): 30000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN(8x8)
ProASIC3 nano Flash FPGAs
Revision 11
2-33
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-44 Minimum and Maximum DC Input and Output Levels
1.8 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL1 IIH2
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3 A4 A4
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
2
9
11
10 10
4 mA
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
4
17
22
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-8 AC Loading
Table 2-45 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
01.8
0.9
10
Notes:
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.
2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
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