Revision 13 5-9 Advance v0.5 (continued) The "I/O User Input/Output" pin description was updated to include" />
參數(shù)資料
型號： A3PE600-PQG208I
廠商： Microsemi SoC
文件頁數(shù)： 67/162頁
文件大?。?/td> 0K
描述： IC FPGA 600000 GATES 208-PQFP
標(biāo)準(zhǔn)包裝： 24
系列： ProASIC3E
RAM 位總計(jì)： 110592
輸入/輸出數(shù)： 147
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
ProASIC3E Flash Family FPGAs
Revision 13
5-9
Advance v0.5
(continued)
The "I/O User Input/Output" pin description was updated to include information on
what happens when the pin is unused.
2-50
The "JTAG Pins" section was updated to include information on what happens
when the pin is unused.
2-51
The "Programming" section was updated to include information concerning
serialization.
2-53
The "JTAG 1532" section was updated to include SAMPLE/PRELOAD
information.
2-54
The "DC and Switching Characteristics" chapter was updated with new
information.
Starting
on page
3-1
Table 3-6 was updated.
3-5
In Table 3-10, PAC4 was updated.
3-8
Table 3-19 was updated.
3-20
The note in Table 3-24 was updated.
3-23
All Timing Characteristics tables were updated from LVTTL to Register Delays
3-26 to
3-64
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
3-74 to
3-79
FTCKMAX was updated in Table 3-98.
3-80
Advance v0.4
(October 2005)
The "Packaging Tables" table was updated.
ii
Advance v0.3
Figure 2-11 was updated.
2-9
The "Clock Resources (VersaNets)" section was updated.
2-9
The "VersaNet Global Networks and Spine Access" section was updated.
2-9
The "PLL Macro" section was updated.
2-15
Figure 2-27 was updated.
2-28
Figure 2-20 was updated.
2-19
Table 2-5 was updated.
2-25
Table 2-6 was updated.
2-25
The "FIFO Flag Usage Considerations" section was updated.
2-27
Table 2-33 was updated.
2-51
Figure 2-24 was updated.
2-31
The "Cold-Sparing Support" section is new.
2-34
Table 2-45 was updated.
2-64
Table 2-48 was updated.
2-81
Pin descriptions in the "JTAG Pins" section were updated.
2-51
The "Pin Descriptions" section was updated.
2-50
Table 3-7 was updated.
3-6
Revision
Changes
Page
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PE600-PQG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-PQG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-PQG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-PQG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE-STARTER-KIT-2 功能描述:KIT EVAL FOR A3PE1500 PROASIC3 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:ProASIC3 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
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