2-42 Revision 13 HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V" />
參數(shù)資料
型號： A3PE600-FG484I
廠商： Microsemi SoC
文件頁數(shù)： 115/162頁
文件大?。?/td> 0K
描述： IC FPGA 600000 GATES 484-FBGA
標(biāo)準包裝： 40
系列： ProASIC3E
RAM 位總計： 110592
輸入/輸出數(shù)： 270
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
ProASIC3E DC and Switching Characteristics
2-42
Revision 13
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull
output buffer.
Timing Characteristics
Table 2-60 Minimum and Maximum DC Input and Output Levels
HSTL Class I
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA1
Max.
mA1
A2 A2
8 mA
–0.3 VREF – 0.1 VREF + 0.1
3.6
0.4
VCCI – 0.4 8
8
39
32
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-16 AC Loading
Table 2-61 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point*
(V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.1
VREF + 0.1
0.75
20
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Test Point
20 pF
50
HSTL
Class I
VTT
Table 2-62 HSTL Class I
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = .4 V, VREF = 0.75 V
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
3.18
0.04
2.12
0.43
3.24
3.14
5.47
5.38
ns
–1
0.56
2.70
0.04
1.81
0.36
2.75
2.67
4.66
4.58
ns
–2
0.49
2.37
0.03
1.59
0.32
2.42
2.35
4.09
4.02
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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