2-80 Revision 13 Figure 2-51 FIFO FULL Flag and AFULL Flag Assertion Figure 2-52 FIFO E" />
參數(shù)資料
型號: A3PE600-FG484
廠商: Microsemi SoC
文件頁數(shù): 157/162頁
文件大?。?/td> 0K
描述: IC FPGA 600000 GATES 484-FBGA
標準包裝: 40
系列: ProASIC3E
RAM 位總計: 110592
輸入/輸出數(shù): 270
門數(shù): 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 484-BGA
供應商設備封裝: 484-FPBGA(23x23)
ProASIC3E DC and Switching Characteristics
2-80
Revision 13
Figure 2-51 FIFO FULL Flag and AFULL Flag Assertion
Figure 2-52 FIFO EMPTY Flag and AEMPTY Flag Deassertion
Figure 2-53 FIFO FULL Flag and AFULL Flag Deassertion
NO MATCH
Dist = AFF_TH
MATCH (FULL)
tCKAF
tWCKFF
tCYC
WCLK
FULL
AFULL
WA/RA
(Address Counter)
WCLK
WA/RA
(Address Counter)
MATCH
(EMPTY)
NO MATCH
Dist = AEF_TH + 1
NO MATCH
RCLK
EMPTY
1st Rising
Edge
After 1st
Write
2nd Rising
Edge
After 1st
Write
tRCKEF
tCKAF
AEMPTY
Dist = AFF_TH – 1
MATCH (FULL)
NO MATCH
tWCKF
tCKAF
1st Rising
Edge
After 1st
Read
1st Rising
Edge
After 2nd
Read
RCLK
WA/RA
(Address Counter)
WCLK
FULL
AFULL
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參數(shù)描述
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