參數(shù)資料
型號(hào)： A3PE600-1PQ208I
廠商： Microsemi SoC
文件頁數(shù)： 59/162頁
文件大?。?/td> 0K
描述： IC FPGA 600000 GATES 208-PQFP
標(biāo)準(zhǔn)包裝： 24
系列： ProASIC3E
RAM 位總計(jì)： 110592
輸入/輸出數(shù)： 147
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
Revision 13
5-1
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the ProASIC3E datasheet.
Revision
Changes
Page
Revision 13
(January 2013)
(CCC) and PLL Wide Input Frequency Range from ’1.5 MHz to 200 MHz’ to
’1.5MHz to 350 MHz’ based on Table 2-98 ProASIC3E CCC/PLL Specification
(SAR 22196).
The "ProASIC3E Ordering Information" section has been updated to mention "Y"
as "Blank" mentioning "Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43220).
The programming temperature range supported is Tambient = 0°C to 85°C.
The note in Table 2-98 ProASIC3E CCC/PLL Specification referring the reader
to SmartGen was revised to refer instead to the online help associated with the
core (SAR 42571).
Libero Integrated Design Environment (IDE) was changed to Libero System-on-
Chip (SoC) throughout the document (SAR 40285).
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
NA
Revision 12
(September 2012)
The "Security" section was modified to clarify that Microsemi does not support
read-back of programmed data.
Revision 11
(August 2012)
Added a Note stating "VMV pins must be connected to the corresponding VCCI pins.
information.
The drive strength, IOL, and IOH value for 3.3 V GTL and 2.5 V GTL was
changed from 25 mA to 20 mA in the following tables (SAR 31924):
Also added note stating "Output drive strength is below JEDEC specification." for
Tables 2-17 and 2-19.
Additionally, the IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were
corrected from 51 to 35 (for 3.3 V GTL+) and from 40 to 33 (for 2.5 V GTL+) in
table Table 2-13 (SAR 39714).
the maximum temperature from 110°C to 100°C, with an example of six months
instead of three months (SAR 37934).
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR
34796):
"It uses a 5 V–tolerant input buffer and push-pull output buffer." This change was
made in revision 10 and omitted from the change table in error.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PE600-1PQ896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-1PQ896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-1PQ896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-1PQ896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-1PQG208 功能描述:IC FPGA 600000 GATES 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
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