2-8 Revision 13 Power Consumption of Various Internal Resources SSTL3 (I) 30 3.3 26.02 114.87 SSTL3 (II" />
參數(shù)資料
型號： A3PE1500-PQ208
廠商： Microsemi SoC
文件頁數(shù)： 78/162頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 1.5M 208-PQFP
標準包裝： 24
系列： ProASIC3E
RAM 位總計： 276480
輸入/輸出數(shù)： 147
門數(shù)： 1500000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
ProASIC3E DC and Switching Characteristics
2-8
Revision 13
Power Consumption of Various Internal Resources
SSTL3 (I)
30
3.3
26.02
114.87
SSTL3 (II)
30
3.3
42.21
131.76
Differential
LVDS/B-LVDS/M-LVDS
–
2.5
7.70
89.62
LVPECL
–
3.3
19.42
168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Table 2-9 Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings (continued)
CLOAD
(pF)
VCCI
(V)
Static Power
PDC3 (mW)2
Dynamic Power
PAC10 (W/MHz)3
Table 2-10 Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices
Parameter
Definition
Device-Specific Dynamic Contributions
(W/MHz)
A3PE600
A3PE1500
A3PE3000
PAC1
Clock contribution of a Global Rib
12.77
16.21
19.7
PAC2
Clock contribution of a Global Spine
1.85
3.06
4.16
PAC3
Clock contribution of a VersaTile row
0.88
PAC4
Clock contribution of a VersaTile used as a sequential
module
0.12
PAC5
First contribution of a VersaTile used as a sequential
module
0.07
PAC6
Second contribution of a VersaTile used as a sequential
module
0.29
PAC7
Contribution of a VersaTile used as a combinatorial
module
0.29
PAC8
Average contribution of a routing net
0.70
PAC9
Contribution of an I/O input pin (standard-dependent)
PAC10
Contribution of an I/O output pin (standard-dependent)
PAC11
Average contribution of a RAM block during a read
operation
25.00
PAC12
Average contribution of a RAM block during a write
operation
30.00
PAC13
Static PLL contribution
2.55 mW
PAC14
Dynamic contribution for PLL
2.60
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
calculator or SmartPower in Libero SoC.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PE1500-PQ208I 功能描述:IC FPGA 1KB FLASH 1.5M 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3E 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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