Revision 13 2-11 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logi" />
參數(shù)資料
型號: A3PE1500-FGG676I
廠商: Microsemi SoC
文件頁數(shù): 81/162頁
文件大小: 0K
描述: IC FPGA 1KB FLASH 1.5M 676-FBGA
標(biāo)準(zhǔn)包裝: 40
系列: ProASIC3E
RAM 位總計(jì): 276480
輸入/輸出數(shù): 444
門數(shù): 1500000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
ProASIC3E Flash Family FPGAs
Revision 13
2-11
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock
frequency.
The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1
= 50%
– Bit 2
= 25%
–…
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-11 Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
1
Toggle rate of VersaTile outputs
10%
2
I/O buffer toggle rate
10%
Table 2-12 Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
1
I/O output buffer enable rate
100%
2
RAM enable rate for read operations
12.5%
3
RAM enable rate for write operations
12.5%
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