2-12 Revision 13 User I/O Characteristics Timing Model Figure 2-2 Timing Model
參數(shù)資料
型號(hào): A3PE1500-1FGG676
廠商: Microsemi SoC
文件頁數(shù): 82/162頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 1.5M 676-FBGA
標(biāo)準(zhǔn)包裝: 40
系列: ProASIC3E
RAM 位總計(jì): 276480
輸入/輸出數(shù): 444
門數(shù): 1500000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
ProASIC3E DC and Switching Characteristics
2-12
Revision 13
User I/O Characteristics
Timing Model
Figure 2-2 Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V
DQ
Y
DQ
Y
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL
LVDS,
BLVDS,
M-LVDS
GTL+ 3.3V
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTL/LVCMOS
Output drive strength = 24 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
LVTTL/LVCMOS
Output drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
tPD = 0.56 ns
tPD = 0.49 ns
tDP = 1.36 ns
tPD = 0.87 ns
tDP = 2.74 ns
tPD = 0.51 ns
tPD = 0.47 ns
tDP = 2.39 ns
tDP = 3.30 ns
tCLKQ = 0.59 ns
tDP = 1.53 ns
tSUD = 0.31 ns
tPY = 0.90 ns
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tPY = 0.90 ns
tPD = 0.47 ns
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tPY = 1.36 ns
tPY = 0.90 ns
tICLKQ = 0.24 ns
tISUD = 0.26 ns
tPY = 1.22 ns
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