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參數(shù)資料
| 型號(hào)： | A3P600 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | ProASIC3 Flash Family FPGAs with Optional Soft ARM Support |
| 中文描述： | 的ProASIC3閃存系列FPGA支持可選軟ARM |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 176K |
| 代理商： | A3P600 |
May 2007
2007 Actel Corporation
1
See the Actel website for the latest version of the datasheet.
ProASIC
3 Flash Family FPGAs
with Optional Soft ARM
Support
Features and Benefits
High Capacity
30 k to 1 Million System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
1 kbit of FlashROM with Synchronous Interfacing
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI (except A3P030)
In-System Programming (ISP) and Security
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except A3P030 and ARM
-
enabled ProASIC
3 devices) via JTAG (IEEE 1532–
compliant)
FlashLock
to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V,3.3 V PCI / 3.3 V PCI-X (except
A3P030), and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os (A3P030 only)
Programmable Output Slew Rate (except A3P030) and
Drive Strength
Weak Pull-Up/Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL (except A3P030)
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback, Multiply/Divide,
Delay Capabilities, and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
CoreMP7Sd (with debug) and CoreMP7S (without debug
SRAMs and FIFOs (except A3P030)
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,
×4, ×9, and ×18 Organizations Available)
True Dual-Port SRAM (except ×18)
24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
Soft ARM7 Core Support in M7 ProASIC3 Devices
CoreMP7Sd (with debug) and CoreMP7S (without
debug)
Table 1
ProASIC3 Devices
ARM
-Enabled
ProASIC3 Devices
1
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
2
Integrated PLL in CCCs
VersaNet Globals
3
I/O Banks
Maximum User I/Os
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
ProASIC3 Product Family
A3P030
A3P060
A3P125
A3P250
A3P400
A3P600
A3P1000
M7A3P250
250 k
6,144
36
8
1 k
Yes
1
18
4
157
M7A3P400
400 k
9,216
54
12
1 k
Yes
1
18
4
194
M7A3P600
600 k
13,824
108
24
1 k
Yes
1
18
4
235
M7A3P1000
1 M
24,576
144
32
1 k
Yes
1
18
4
300
30 k
768
–
–
1 k
–
–
6
2
81
60 k
1,536
18
4
1 k
Yes
1
18
2
96
125 k
3,072
36
8
1 k
Yes
1
18
2
133
QN132
VQ100
QN132
VQ100
TQ144
FG144
QN132
VQ100
TQ144
PQ208
FG144
QN132
5
VQ100
PQ208
FG144,
FG256
5
PQ208
FG144, FG256,
FG484
PQ208
FG144, FG256,
FG484
PQ208
FG144, FG256,
FG484
Notes:
1.
2.
3.
4.
5.
Refer to the
CoreMP7
datasheet for more information.
AES is not available for ARM-enabled ProASIC3 devices.
Six chip (main) and three quadrant global networks are available for A3P060 and above.
For higher densities and support of additional features, refer to the
ProASIC3E Flash FPGAs
datasheet.
The M7A3P250 device does not support this package.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3P600-1FG144 | 功能描述:IC FPGA 1KB FLASH 600K 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A3P600-1FG144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P600-1FG144I | 功能描述:IC FPGA 1KB FLASH 600K 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A3P600-1FG144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P600-1FG256 | 功能描述:IC FPGA 1KB FLASH 600K 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
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