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參數(shù)資料
| 型號(hào)： | A3P250-VQG100T |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 132/220頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 1KB FLASH 250K 100-VQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ProASIC3 |
| RAM 位總計(jì)： | 36864 |
| 輸入/輸出數(shù)： | 68 |
| 門(mén)數(shù)： | 250000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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ProASIC3 Flash Family FPGAs
Revision 13
5-11
Advance v0.3
The "PLL Macro" section was updated. EXTFB information was removed from
this section.
2-15
The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 2-
11 ProASIC3 CCC/PLL Specification
2-29
EXTFB was removed from Figure 2-27 CCC/PLL Macro.
2-28
Table 2-13 ProASIC3 I/O Features was updated.
2-30
The "Hot-Swap Support" section was updated.
2-33
The "Cold-Sparing Support" section was updated.
2-34
"Electrostatic Discharge (ESD) Protection" section was updated.
2-35
The LVPECL specification in Table 2-43 I/O Hot-Swap and 5 V Input Tolerance
Capabilities in ProASIC3 Devices was updated.
2-64
In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and VCCIB2 was
changed to VCCIB1.
2-97
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section.
2-50
The "JTAG Pins" section was updated.
2-51
"128-Bit AES Decryption" section was updated to include M7 device information.
2-53
Table 3-6 was updated.
3-6
Table 3-7 was updated.
3-6
In Table 3-11, PAC4 was updated.
3-93-8
Table 3-20 was updated.
3-20
The note in Table 3-32 was updated.
3-27
All Timing Characteristics tables were updated from LVTTL to Register Delays
3-31 to 3-
73
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
3-85 to
3-90
FTCKMAX was updated in Table 3-110.
3-97
Advance v0.2
Figure 2-11 was updated.
2-9
The "Clock Resources (VersaNets)" section was updated.
2-9
The "VersaNet Global Networks and Spine Access" section was updated.
2-9
The "PLL Macro" section was updated.
2-15
Figure 2-27 was updated.
2-28
Figure 2-20 was updated.
2-19
Table 2-5 was updated.
2-25
Table 2-6 was updated.
2-25
The "FIFO Flag Usage Considerations" section was updated.
2-27
Table 2-13 was updated.
2-30
Figure 2-24 was updated.
2-31
The "Cold-Sparing Support" section is new.
2-34
Revision
Changes
Page
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3P250-VQG144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P250-VQG144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P250-VQG144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P250-VQG144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P250-VQG144T | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Automotive ProASIC3 Flash Family FPGAs |
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