參數(shù)資料
型號(hào)： A3P125-VQG100II
元件分類： FPGA
英文描述： FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, VQFP-100
文件頁(yè)數(shù)： 2/49頁(yè)
文件大?。?/td> 5893K
代理商： A3P125-VQG100II
ProASIC3 DC and Switching Characteristics
v1.3
2 - 83
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-106 ProASIC3 CCC/PLL Specification
Parameter
Minimum
Typical
Maximum
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
Serial Clock (SCLK) for Dynamic PLL1
125
MHz
Delay Increments in Programmable Delay Blocks2, 3
200
ps
Number of Programmable Values in Each Programmable
Delay Block
32
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
0.50%
0.70%
24 MHz to 100 MHz
1.00%
1.20%
100 MHz to 250 MHz
1.75%
2.00%
250 MHz to 350 MHz
2.50%
5.60%
Acquisition Time
(A3P250 and A3P1000 only)
LockControl = 0
300
s
LockControl = 1
300
s
(all other dies)
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter 5
(A3P250 and A3P1000 only)
LockControl = 0
1.6
ns
LockControl = 1
1.6
ns
(all other dies)
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 12, 3
0.6
5.56
ns
Delay Range in Block: Programmable Delay 22, 3
0.025
5.56
ns
Delay Range in Block: Fixed Delay2, 3
2.2
ns
Notes:
1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific
junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings.
3. TJ = 25°C, VCC = 1.5 V
4. The A3P030 device does not contain a PLL.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL
input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by
the period jitter parameter.
相關(guān)PDF資料
PDF描述
A42MX36-3PQG208B FPGA, 2438 CLBS, 36000 GATES, PQFP208
A3P030-FQN132 FPGA, 768 CLBS, 30000 GATES, 350 MHz, BCC132
A3P030-FVQ100 FPGA, 768 CLBS, 30000 GATES, 350 MHz, PQFP100
A3P125-FFG144 FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PBGA144
A3P125-FPQ208 FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3P125-VQG100IPT72 制造商:Microsemi SOC Products Group 功能描述:ACLA3P125-VQG100IPT72 125K GATES 231MHZ
A3P125-VQG100T 功能描述:IC FPGA 1KB FLASH 125K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3P125-VQG144 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
A3P125-VQG144ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
A3P125-VQG144I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*