參數(shù)資料
型號(hào)： A3P125-FTQG144
元件分類： FPGA
英文描述： FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, GREEN, TQFP-144
文件頁數(shù)： 46/49頁
文件大?。?/td> 5893K
代理商： A3P125-FTQG144
ProASIC3 DC and Switching Characteristics
v1.3
2 - 79
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be
driven and conditioned internally by the CCC module. For more details on clock conditioning
Table 2-105 on page 2-82 present minimum and maximum global clock delays within each device.
Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
Table 2-98 A3P015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.66
0.81
0.75
0.92
0.88
1.08
1.06
1.30
ns
tRCKH
Input HIGH Delay for Global Clock
0.67
0.84
0.76
0.96
0.89
1.13
1.07
1.36
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.18
0.21
0.25
0.30
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-99 A3P030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.67 0.81 0.76 0.92 0.89 1.09 1.07 1.31
ns
tRCKH
Input HIGH Delay for Global Clock
0.680.85 0.770.970.911.141.091.37
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.18
0.21
0.24
0.29
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
相關(guān)PDF資料
PDF描述
A3P125-FVQG100 FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100
A42MX36-1BGG304 FPGA, 2438 CLBS, 36000 GATES, PBGA304
A42MX36-1BGG304I FPGA, 2438 CLBS, 36000 GATES, PBGA304
A42MX36-1RQG240 FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP240
A42MX36-1RQG240I FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP240
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3P125-FVQ100 制造商:Microsemi Corporation 功能描述:FPGA PROASIC3 125K GATES 193MHZ COMM 130NM 1.5V 100VQFP - Trays
A3P125-FVQ144 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
A3P125-FVQ144ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
A3P125-FVQ144I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
A3P125-FVQ144PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*