- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄209983 > A3P125-FPQ208 FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP208 PDF資料下載
參數(shù)資料
| 型號(hào)： | A3P125-FPQ208 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP208 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 25/49頁(yè) |
| 文件大?。?/td> | 5893K |
| 代理商： | A3P125-FPQ208 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)當(dāng)前第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)
ProASIC3 DC and Switching Characteristics
2- 104
v1.3
Part Number and Revision Date
Part Number 51700097-002-3
Revised August 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version
Changes in Current Version (v1.3)
Page
v1.2
(June 2008)
TJ, Maximum Junction Temperature, was changed to 100° from 110 in the
"Thermal Characteristics" section and EQ 2-2. The calculated result of Maximum
Power Allowed has thus changed to 1.463 W from 1.951 W.
Values for the A3P015 device were added to Table 2-7 Quiescent Supply
Values for the A3P015 device were added to Table 2-14 Different Components
Consumption in ProASIC3 Devices is new.
from PAC13 + PAC14 * FCLKOUT to PDC4 + PAC13 * FCLKOUT.
Both fall and rise values were included for tDDRISUD and tDDRIHD in
The typical value for Delay Increments in Programmable Delay Blocks was
changed from 160 to 200 in Table 2-106 ProASIC3 CCC/PLL Specification.
v1.1
(January 2008)
Table note references were added to Table 2-2 Recommended Operating
Conditions 1, and the order of the table notes was changed.
The title for Table 2-4 Overshoot and Undershoot Limits 1 was modified to
remove "as measured on quiet I/Os." Table note 1 was revised to remove
"estimated SSO density over cycles." Table note 2 was revised to remove "refers
only to overshoot/undershoot limits for simultaneous switching I/Os.
"
The "Power per I/O Pin" section was updated to include 3 additional tables
pertaining to input buffer power and output buffer power.
Table 2-29 I/O Output Buffer Maximum Resistances 1 was revised to include
values for 3.3 V PCI/PCI-X.
updated.
v1.0
(January 2008)
column and was incorrect. It was corrected and changed to TA.
Temperature1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
The "PLL Behavior at Brownout Condition" section is new.
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency.
was incorrect. It previously said TJ and it was corrected and changed to TA.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A3P125-FTQ144 | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP144 |
| A3P125-FVQ100 | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100 |
| A3P030-FQNG132 | FPGA, 768 CLBS, 30000 GATES, 350 MHz, BCC132 |
| A3P030-FVQG100 | FPGA, 768 CLBS, 30000 GATES, 350 MHz, PQFP100 |
| A3P125-FFGG144 | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3P125-FPQG144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-FPQG144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-FPQG144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-FPQG144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-FPQG208 | 制造商:Microsemi Corporation 功能描述:FPGA PROASIC3 125K GATES 193MHZ COMM 130NM 1.5V 208PQFP - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。