
FlashROM in Actel’s Low-Power Flash Devices
5- 8
v1.1
FlashROM Design Flow
The Actel Libero Integrated Design Environment (IDE) software has extensive FlashROM support,
including FlashROM generation, instantiation, simulation, and programming.
Figure 5-9 shows the
user flow diagram. In the design flow, there are three main steps:
1. FlashROM generation and instantiation in the design
2. Simulation of FlashROM design
3. Programming file generation for FlashROM design
FlashROM Generation and Instantiation in the Design
The SmartGen core generator, available in Libero IDE and Designer, is the only tool that can be used
to generate the FlashROM content. SmartGen has several user-friendly features to help generate
the FlashROM contents. Instead of selecting each byte and assigning values, you can create a
region within a page, modify the region, and assign properties to that region. The FlashROM user
and properties field. The properties field specifies the region-specific information and defines the
data used for that region. You can assign values to the following properties:
1. Static Fixed Data—Enables you to fix the data so it cannot be changed during programming
time. This option is useful when you have fixed data stored in this region, which is required
for the operation of the design in the FPGA. Key storage is one example.
2. Static Modifiable Data—Select this option when the data in a particular region is expected
to be static data (such as a version number, which remains the same for a long duration but
could conceivably change in the future). This option enables you to avoid changing the
value every time you enter new data.
Figure 5-9 FlashROM Design Flow
Simulator
FlashPoint
SmartGen
Programmer
Synthesis
Designer
Security
Header
Options
Programming
Files
UFC
File
FlashROM
Netlist
User
Design
User
Netlist
Core
Map
MEM
File
Back-
Annotated
Netlist